DC Accurate Noise Compatible Reduced Netlist Synthesis
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Solution Overview
Problem
Current model-order reduction algorithms for electronic circuits, such as PRIMA and SPRIM, fail to preserve block structures and input/output incidence matrices, leading to noise-incompatible and inaccurately synthesized netlists with negative resistors, especially at DC analysis.
Innovation Solution
The proposed method involves a circuit analysis system that generates a reduced model using PRIMA, applies structure and I/O preservation techniques like IOPOR, and performs a positive netlist synthesis with no controlled sources, ensuring the netlist is noise-compatible and accurate at DC through dynamic susceptance filtering and ideal transformer substitution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If model-order reduction algorithms (PRIMA, SPRIM) are used to reduce netlist size, then simulation speed is improved, but the synthesized netlist becomes noise-incompatible and inaccurate at DC analysis
Solution Approach 1:
The patent segments the synthesis process into distinct phases: structure-preserving model-order reduction to generate initial reduced netlist, followed by separate DC accuracy correction and noise compatibility correction phases. This segmentation allows each phase to optimize for its specific goal without compromising the other.
Solution Approach 2:
The patent introduces intermediate correction steps as mediators between the model-order reduction process and final simulation. The DC correction module and noise compatibility module act as intermediaries that refine the reduced netlist, adding controlled sources and adjusting parameters to restore accuracy while maintaining the benefits of reduction.
2Stability of the object's composition
If structure-preserving model-order reduction (IOPOR) is applied, then block structure is preserved, but the netlist still contains negative resistors and controlled sources that cause noise incompatibility
Solution Approach 1:
The patent converts the harmful effect of negative resistors and controlled sources into a benefit by systematically identifying and correcting them in a dedicated noise compatibility correction phase. The controlled sources that initially cause noise incompatibility are detected and replaced with equivalent passive structures that maintain electrical behavior while ensuring noise compatibility.
Solution Approach 2:
The patent changes parameters of the reduced netlist elements during the noise compatibility correction phase, specifically modifying resistance values to eliminate negative resistors and adjusting controlled source parameters or replacing them entirely. This parameter transformation maintains the block structure while achieving noise compatibility.
3Reliability
If positive netlist synthesis is performed without controlled sources, then noise compatibility is achieved, but DC accuracy may be compromised
Solution Approach 1:
The patent performs preliminary DC correction before the noise compatibility correction phase. By establishing DC accuracy early in the process and then maintaining it through subsequent transformations, the final positive netlist synthesis can achieve noise compatibility without sacrificing the previously established DC accuracy.
Solution Approach 2:
The patent implements feedback mechanisms where each correction phase (DC correction, noise compatibility correction) validates and adjusts the results of previous phases. The DC correction phase provides feedback to ensure accuracy is maintained, and the noise compatibility phase provides feedback to verify that positive element synthesis does not degrade DC performance.
Data Source
AI summary
In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.