DC Bus Voltage Balancing Circuit With Depletion-Mode FET Discharge
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Solution Overview
Problem
In power conversion systems with high voltage DC bus circuits, existing technologies face challenges in balancing and quickly discharging DC bus capacitors due to varying insulation resistance of electrolytic capacitors, leading to leakage current and inefficient discharge processes.
Innovation Solution
A system utilizing depletion mode field effect transistors (FETs) and a control circuit to balance and discharge DC bus capacitors by sensing voltage differences and controlling the FETs to equalize capacitor voltages and facilitate rapid discharge when the power supply is off or below a threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If electrolytic capacitors are used in DC bus circuits, then capacitance and energy storage are improved, but insulation resistance varies leading to leakage current and voltage imbalance
Solution Approach 1:
The patent implements a feedback control system using voltage sense circuits to continuously monitor capacitor voltages and a control circuit that adjusts the switching states of depletion mode FETs based on voltage differences. When voltage imbalance is detected, the control circuit activates appropriate FETs to equalize voltages, creating a closed-loop feedback mechanism that maintains voltage balance despite variations in insulation resistance
Solution Approach 2:
The patent introduces depletion mode FETs as intermediary components between the capacitors and the balancing control system. These FETs act as controllable conductive paths that the control circuit can activate to equalize voltages across capacitors, serving as mediators that enable voltage balancing without directly modifying the capacitor characteristics
2Reliability
If traditional discharge methods are used, then safety is maintained, but discharge time is long and maintenance wait time increases
Solution Approach 1:
The patent employs dynamic discharge control using depletion mode FETs whose conductivity can be rapidly adjusted by the control circuit. Unlike fixed resistance discharge paths, the FETs provide a dynamically controllable discharge path that can be activated or deactivated based on real-time voltage conditions, enabling fast initial discharge followed by controlled completion discharge for safety
Solution Approach 2:
The patent implements periodic monitoring and controlled discharge actions through the control circuit that periodically checks capacitor voltages and activates discharge paths when needed. The system alternates between monitoring mode and active discharge mode, creating periodic action that ensures both fast discharge when required and safety through controlled discharge phases
3Speed
If depletion mode FETs are used for balancing, then voltage balancing speed is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the inherent characteristics of depletion mode FETs that automatically conduct when gate-source voltage is zero or negative, eliminating the need for complex gate drive circuits. The FETs essentially self-regulate their conduction state based on the voltage conditions at their terminals, reducing the complexity of control circuitry while maintaining fast balancing response
Solution Approach 2:
The depletion mode FETs in the patent serve multiple functions: they act as switching elements for voltage balancing, provide discharge paths for capacitor energy dissipation, and function as controllable resistors for voltage equalization. This multi-functionality reduces the need for separate components for each function, thereby reducing overall device complexity despite the enhanced capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves efficient voltage balancing and rapid discharge of DC bus capacitors, reducing maintenance wait times and improving energy efficiency compared to traditional methods, with faster discharge times and lower heat dissipation.
Implementation Method 1
a voltage sense circuit configured to sense a first capacitor voltage of the first bus capacitor and a second capacitor voltage of the second bus capacitor
Implementation Method 2
The first depletion mode field effect transistor (FET) is coupled between the first bus capacitor and a first switching control circuit
Data Source
AI summary
A system has a DC bus circuit with first and second terminals, an intermediate node, first and second capacitors, first and second depletion mode FETs, and first and second switching control circuits, where the first depletion mode FET has a drain coupled to the first bus terminal, a source, and a gate coupled to the intermediate node, the second depletion mode FET has a drain coupled to the intermediate node, a source, and a gate coupled to the second bus terminal, the first switching control circuit turns the first depletion mode FET off responsive to a first capacitor voltage of the first bus capacitor being less than or equal to a second capacitor voltage of the second bus capacitor, and the second switching control circuit turns the second depletion mode FET off responsive to the first capacitor voltage being greater than or equal to the second capacitor voltage.