DC Converter PFM Mode Detection via Drain-to-Source Voltage Sampling
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Solution Overview
Problem
Conventional power converters experience inefficiencies and mode bouncing between PWM and PFM modes due to inaccurate detection of load current levels and inductor current ripples, leading to reduced efficiency and increased output voltage ripple.
Innovation Solution
A switch mode control circuit that samples the drain-to-source voltage of a low-side transistor and compares it to a threshold to determine the presence of negative inductor current, allowing the power converter to switch from PWM to PFM mode, thereby improving efficiency and reducing mode bouncing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional power converters use traditional detection methods to determine PFM mode entry, then the device complexity is reduced, but the measurement precision of load current levels and inductor current ripples deteriorates, causing mode bouncing and reduced efficiency
Solution Approach 1:
The patent uses the drain-to-source voltage of the low-side transistor as an intermediary signal to indirectly detect negative inductor current. Instead of directly measuring inductor current, the circuit monitors the voltage across the low-side transistor, which naturally reflects the current state. This intermediary approach achieves accurate detection without requiring complex current sensing circuitry.
Solution Approach 2:
The low-side transistor's own drain-to-source voltage is utilized to provide detection information about the inductor current state. The transistor's inherent electrical characteristics serve the dual purpose of current conduction and mode detection, eliminating the need for separate detection components and reducing overall circuit complexity.
2Adaptability or versatility
If the power converter switches between PWM and PFM modes based on inaccurate detection, then the adaptability to different load conditions is improved, but the loss of energy increases due to mode bouncing and reduced efficiency
Solution Approach 1:
The patent implements a feedback mechanism where the drain-to-source voltage of the low-side transistor is continuously monitored and fed back to the control circuit. This feedback allows the system to accurately determine when to switch between PWM and PFM modes based on the actual current state, preventing premature or incorrect mode transitions that would cause energy loss.
Solution Approach 2:
The detection circuit proactively identifies the conditions for PFM mode entry by monitoring the drain-to-source voltage before mode switching occurs. By detecting negative inductor current in advance, the system can smoothly transition to PFM mode at the optimal moment, avoiding energy losses associated with delayed or incorrect mode changes.
3Productivity
If conventional detection methods are used to determine PFM mode entry, then the ease of operation is maintained, but the productivity of the power converter deteriorates due to increased output voltage ripple and reduced efficiency
Solution Approach 1:
The low-side transistor serves multiple functions: it conducts current during the switching cycle and simultaneously provides detection information through its drain-to-source voltage. This multi-functional approach enables accurate mode detection without adding separate operational complexities, maintaining ease of operation while improving productivity.
Solution Approach 2:
The patent merges the current conduction function of the low-side transistor with the mode detection function. By combining these two functions into a single component and measurement approach, the system achieves improved efficiency without increasing operational complexity, as the same circuit elements serve dual purposes.
Data Source
AI summary
Methods, apparatus, systems and articles of manufacture are disclosed to adjust an operating mode of a power converter. An example apparatus includes a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter, a capacitor coupled to the second current terminal, a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal, a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal, a multiplexer coupled to the comparator output, a first flip-flop coupled to the multiplexer and the second logic gate input, and a second flip-flop coupled to the multiplexer and the first flip-flop.