DC-Coupled High-Gain Amplifier With Wideband Bias Reduction
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Solution Overview
Problem
Existing distributed amplifiers and voltage-controlled attenuators face limitations in achieving high gain and bandwidth while maintaining a compact size, often requiring larger FETs or reducing bandwidth, and suffer from limited dynamic range and linearity due to the size constraints of single FETs.
Innovation Solution
The implementation of a pre-driver section with mirrored transistors and a current source, along with a voltage divider network using resistors and capacitors, enhances signal amplification and reduces DC bias voltage, allowing for increased gain and flat frequency response across a wide bandwidth. Additionally, using cascode configured transistors and interstage inductors with capacitors increases cut-off frequency and maintains linearity by distributing voltage swings across multiple FETs in voltage-controlled attenuators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If larger FETs are used to achieve high gain, then gain is improved, but device area increases
Solution Approach 1:
The amplifier is divided into multiple distributed amplifier sections, each with its own FET. By segmenting the amplification function across multiple smaller FETs rather than using one large FET, the patent achieves high cumulative gain while maintaining compact individual device sizes. The multiple sections are connected through inductors to create a distributed amplification structure.
Solution Approach 2:
Multiple amplifier sections are merged into a single distributed amplifier structure where the individual sections work together to provide cumulative gain. The inductors connecting the sections merge the signal paths to achieve high overall gain equivalent to what would require a much larger single FET.
2Power
If more amplifier sections are added to increase gain, then gain is improved, but device complexity increases
Solution Approach 1:
Each amplifier section uses the same standardized FET configuration and component layout. This universal design allows multiple sections to be added to increase gain without proportionally increasing complexity, as each section is a replicated module with consistent design rules and impedance matching.
3Area of stationary object
If FET size is reduced to maintain compact design, then device area is reduced, but bandwidth is reduced
Solution Approach 1:
The patent transitions from a single-dimensional approach (one large FET) to a multi-dimensional distributed structure where multiple small FETs are arranged in series through inductive coupling. This dimensional change allows the system to achieve high gain and maintain bandwidth simultaneously by distributing the amplification function across multiple elements rather than concentrating it in one device.
4Area of stationary object
If single FET is used to achieve compact design, then device area is reduced, but dynamic range and linearity are limited
Solution Approach 1:
The amplification function is segmented across multiple FETs in separate amplifier sections. Each FET operates within its linear region, and the cumulative effect of multiple sections provides extended dynamic range and improved linearity compared to a single FET operating near its limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher gain and bandwidth in a compact, energy-efficient design without increasing FET size, while maintaining or improving linearity and dynamic range by distributing voltage swings across multiple FETs, thus overcoming the limitations of prior art.
Implementation Method 1
The FETs 150, 154 of the amplifiers sections 112 have parasitic capacitance and the inductors 108A, 108B, 120A, 120B arranged in the circuit are selected to cancel or counter the parasitic capacitance associated with the amplifier sections
Implementation Method 2
the pre-driver is configured to receive the one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals
Implementation Method 3
the voltage divider network is configured to receive the one or more pre-amplified signals and reduce a DC bias voltage of the one or more pre-amplified signals while achieving a flat gain response across the frequency band of operation
Implementation Method 4
using cascode configured transistors and interstage inductors with capacitors increases cut-off frequency and maintains linearity by distributing voltage swings across multiple FETs
Implementation Method 5
interstage connects the pre-driver to the amplifier such that the interstage is configured with one or more inductors. The interstage further includes one or more capacitors
Data Source
AI summary
An amplifier system with high gain, compact size, and extended bandwidth is disclosed. The amplifier system includes one or more inputs configured to receive one or more input signals and a pre-driver configured to receive the one or more input signals. The pre-driver may comprise source connected FETs which create a virtual ground and may include inductors which cancel or counter parasitic capacitance of the FETs. The pre-driver amplifies the one or more input signals to create one or more pre-amplified signals, which are provided to a voltage divider network configured to reduce a DC bias voltage of the one or more pre-amplified signals, while maintaining a wide bandwidth range. An amplifier receives and amplifies the output of the voltage divider network to create amplified signals. The amplifier may comprise mirrored FET pairs in a common source configuration and a common gate arrangement.