DC-Coupled Level Translator for Fast CMOS Voltage Shifting
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Solution Overview
Problem
There is a need for a high-speed logic level translator that can efficiently translate signals between incompatible voltage rails, particularly for high-speed, high-current CMOS drivers used in applications like medical ultrasound and non-destructive testing, where MOSFET power transistors must be driven quickly with signals from low voltage logic circuits.
Innovation Solution
A fast DC coupled level translator is designed using an inverter comprising transistors with complementary conductivity, capacitors for high-frequency signal transmission, and clamp circuits to limit gate voltages, along with current mirrors to detect input signal relationships and control transistor operation, enabling fast signal translation across different supply voltage groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional logic level translator is used to translate signals between incompatible voltage rails, then voltage level compatibility is achieved, but signal transition speed deteriorates
Solution Approach 1:
The translator is divided into two independent signal paths: a DC-coupled path for low-frequency signals and an AC-coupled path for high-frequency signals. Each path is optimized for its frequency range, allowing the system to maintain both voltage compatibility and high-speed performance across the entire frequency spectrum.
Solution Approach 2:
Capacitors are introduced as intermediary elements in the AC-coupled path to block DC components while allowing AC signals to pass. This enables high-frequency signals to be transmitted without being affected by the DC voltage level differences between the two voltage rails.
2Speed
If AC coupling is used to maintain high-speed signal transmission, then signal transition speed is preserved, but DC signal transmission capability is lost
Solution Approach 1:
The patent merges DC-coupled and AC-coupled translator circuits into a single unified device. The DC-coupled path handles low-frequency and DC signals, while the AC-coupled path handles high-frequency signals. Both paths work simultaneously to provide full-frequency-range translation capability.
Solution Approach 2:
The translator is designed to handle multiple signal types (DC and AC) through multiple parallel paths, making it a universal solution that can translate any frequency range between incompatible voltage rails, rather than being specialized for only one frequency range.
3Productivity
If high current drive capability is added to drive MOSFET power transistors quickly, then switching speed improves, but device complexity increases
Solution Approach 1:
The patent replaces complex multi-stage amplifier circuits with a direct DC-coupled translation path that provides high current drive capability inherently through proper transistor sizing and configuration. This eliminates the need for additional buffering stages while maintaining high-speed MOSFET switching.
Data Source
AI summary
A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor. A second clamp circuit is used for limiting a gate voltage of said second transistor.