DC-DC Converter Adaptive Minimum On-Time Gate Driver
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Solution Overview
Problem
Existing DC-DC converters face issues with shoot-through and loss of stability due to inadequate drive signal timing between high-side and low-side transistors, caused by propagation delays in gate driver circuits, leading to inefficiencies and potential transistor damage.
Innovation Solution
A gate driver circuit is designed with a minimum pulse width control mechanism that adapts the pulse width of drive signals for high-side and low-side transistors based on the propagation delay of the respective gate driver circuits, ensuring appropriate timing to prevent shoot-through and maintain converter stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate driver circuit uses a string of inverters to generate high-current drive signals, then the drive signal strength is sufficient to charge gate capacitances, but the propagation delay increases causing shoot-through and loss of stability
Solution Approach 1:
The gate driver circuit is divided into separate drive paths for high-side and low-side transistors, each with independently optimized inverter strings. The circuit is segmented into enable signal processing, drive signal generation, and minimum pulse width control sections, allowing each segment to be optimized for its specific function without compromising overall performance
Solution Approach 2:
The minimum pulse width control circuit dynamically adjusts the pulse width of drive signals based on the propagation delay characteristics of the gate driver circuit. This dynamic adaptation ensures that the drive signals maintain sufficient strength while preventing shoot-through by compensating for propagation delays in real-time
2Reliability
If the pulse width of drive signals is increased to account for propagation delay, then shoot-through is prevented, but the switching speed and converter efficiency decrease
Solution Approach 1:
The minimum pulse width control circuit incorporates feedback from the propagation delay characteristics of the gate driver circuit to dynamically adjust drive signal timing. This feedback mechanism ensures that pulse widths are optimized for each switching event, preventing shoot-through while maintaining high switching speed and converter efficiency
Solution Approach 2:
The circuit changes the pulse width parameter of drive signals adaptively based on propagation delay measurements. By adjusting this critical parameter in real-time, the system maintains converter stability without sacrificing switching speed or efficiency
3Power
If the gate driver circuit uses multiple inverters in series, then the drive signal current is amplified, but the circuit complexity and propagation delay increase
Solution Approach 1:
The driver circuit is segmented into modular sections with dedicated inverter strings for high-side and low-side transistor control. This segmentation allows each section to use the minimum necessary number of inverters, reducing overall circuit complexity while maintaining sufficient drive current through targeted current amplification where needed
Data Source
AI summary
A DC-DC converter has a high-side transistor series with a low-side transistor and an inductor connected to a node therebetween, a gate driver circuit has a high-side gate driver circuit coupled to the high-side transistor; a low-side gate driver circuit coupled to the low-side transistor; a minimum pulse with circuit coupled to one of the high-side and low-side gate, the minimum pulse width circuit adaptively controlling a pulse width of a drive signal to the high-side or low-side transistor by the propagation delay of the respective gate driver circuit.