Switched-mode DC/DC Converter Bootstrapped High-side Driver
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Solution Overview
Problem
In switched-mode DC/DC converters, the transition of the switch-node from a low state to a high state induces high frequency noise, which is a concern for electromagnetic interference (EMI), and existing techniques to reduce this noise often introduce other issues such as cross-conduction and difficulty in controlling the switch-node slope.
Innovation Solution
A switch-node rising edge detection circuit is introduced to determine when the switch-node reaches a high state before activating the high-side NMOS transistor, using an AND gate, PMOS transistor, inverter, and NMOS transistor configuration to selectively couple the bootstrap capacitor and switch-node, allowing controlled activation of the high-side gate-driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bootstrapped gate-driver is used for the high-side NMOS transistor, then the converter can operate with two NMOS transistors, but cross-conduction may occur between the low-side and high-side switches
Solution Approach 1:
The rising edge detection circuit activates the high-side NMOS transistor only after detecting that the switch-node has reached the high state. This preliminary detection ensures the low-side transistor is fully off before the high-side transistor turns on, preventing cross-conduction while maintaining the bootstrapped gate-driver configuration
Solution Approach 2:
The detection circuit continuously monitors the switch-node voltage and provides feedback control for the high-side transistor activation. This feedback mechanism ensures proper timing and prevents cross-conduction by dynamically adjusting the gate-driver activation based on real-time switch-node conditions
2Speed
If the high-side NMOS transistor is activated early, then the switching speed increases, but high frequency noise and EMI increase
Solution Approach 1:
The detection circuit prepares the high-side transistor activation in advance by monitoring the switch-node voltage, but delays actual activation until the optimal moment when the switch-node reaches the high state. This preliminary preparation without premature activation reduces noise while maintaining fast switching response
Solution Approach 2:
The patent replaces traditional fixed-timing or voltage-threshold-based gate-driver activation with a dynamic detection mechanism that responds to the actual switch-node voltage waveform. This substitution allows optimal timing that minimizes EMI while maintaining switching speed
3Reliability
If a fixed non-overlap time is used between low-side and high-side switches, then cross-conduction is prevented, but the switch-node slope control becomes inflexible
Solution Approach 1:
The patent replaces fixed non-overlap timing with a dynamic detection-based activation mechanism. The high-side transistor activation timing adapts to the actual switch-node voltage waveform, providing flexible slope control while maintaining reliable cross-conduction prevention through real-time conditions monitoring
4Productivity
If the switch-node transitions quickly from low to high state, then switching efficiency improves, but EMI increases
Solution Approach 1:
The detection circuit prepares for the transition by monitoring the switch-node voltage in advance, allowing the system to respond quickly when the high state is reached. This preliminary monitoring enables fast switching efficiency while controlling the actual transition slope to minimize EMI
Data Source
AI summary
A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.