ESD Protection for DC/DC Converter Switches
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Solution Overview
Problem
Existing ESD protection solutions for integrated DC/DC converter switches are inefficient, area-consuming, and difficult to simulate or port between different manufacturing processes, due to their process dependency and reliance on special layout techniques.
Innovation Solution
The implementation of a dual-clamp transistor structure, where a clamp transistor is coupled in parallel to the switching transistor to handle ESD events, reducing the width requirements of the switching transistors and eliminating the need for special layout techniques, while using parasitic devices for activation and control circuitry to manage ESD events efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If un-silicidation technique is used to provide ESD protection for integrated transistors, then ESD protection is improved, but transistor area is considerably increased
Solution Approach 1:
The ESD protection function is segmented from the main switching transistor by adding a separate clamp transistor. The clamp transistor handles ESD current independently, allowing the main switching transistor to maintain its original compact dimensions while still providing ESD protection through the dedicated clamp device.
Solution Approach 2:
The clamp transistor acts as an intermediary device between the switching transistor and the ESD stress. It provides a controlled path for ESD current, protecting the main switching transistor without requiring modifications to its structure that would increase area.
2Reliability
If ballast distributed resistors are added between source/gate and drain/gate, then ESD protection is provided, but layout complexity increases and process portability decreases
Solution Approach 1:
The ESD protection is implemented as a separate clamp transistor rather than modifying the layout of the main transistor with distributed resistors. This segmentation simplifies the layout process and eliminates the need for complex ballast resistor arrangements that are sensitive to process variations.
Solution Approach 2:
The invention changes the approach from modifying resistance parameters within the transistor structure to adding a parallel clamp device with controlled parameters. This allows standard layout techniques to be used without the complex process-dependent resistor implementations.
3Reliability
If gate to drain distance is increased to add ballast resistor, then ESD protection is improved, but transistor area is increased
Solution Approach 1:
The ballast function is segmented from the main transistor by implementing it as a separate clamp transistor with its own channel. This allows the main transistor to maintain minimal gate-to-drain distance for compact area, while the clamp transistor provides the necessary ballast effect for ESD protection.
4Reliability
If special layout techniques are used for ESD protection, then ESD protection is provided, but portability between different manufacturing processes decreases
Solution Approach 1:
The clamp transistor implementation provides a universal ESD protection mechanism that functions across different CMOS processes without requiring process-specific layout techniques. The standard transistor structure and parallel connection approach can be ported between different manufacturing processes, unlike process-dependent ballast resistor implementations.
Data Source
AI summary
The present invention relates to an electronic device including electronic circuitry, wherein the circuitry includes a first switching transistor (MN1) being adapted to serve as an integrated switch, and a first clamp transistor (MNC1) being coupled to the first switching transistor and being adapted to protect the first switching transistor (MN1) if an ESD event occurs.