DC-DC Converter Soft Start Time Adjustment via Digital Accumulator
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Solution Overview
Problem
Existing DC-DC converters face challenges in adjusting the soft start time due to the steep time gradient of the analog signal, which requires changing the circuit configuration of the counter circuit and DA converter, making it difficult to adjust during actual use and resulting in increased circuit size.
Innovation Solution
A DC-DC converter design that includes a frequency divider, accumulator, and DA converter, allowing for flexible adjustment of the soft start time by varying the frequency division ratio and using an accumulator to perform adding operations, enabling the generation of a soft start signal without changing the circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the circuit configuration of the counter circuit and DA converter is changed to adjust the soft start time, then the soft start time can be adjusted, but the circuit size increases and it becomes difficult to adjust during actual use
Solution Approach 1:
The patent changes the adjustment parameter from circuit configuration (resistor values, counter circuit structure) to digital data values stored in a register. By modifying the number of clock cycles counted (stored as digital data), the soft start time can be adjusted without changing the physical circuit configuration. This allows flexible adjustment during actual use simply by writing different data values to the register, thereby improving adaptability while reducing device complexity.
2Adaptability or versatility
If the circuit configuration is modified to adjust the soft start time, then the soft start time can be optimized, but the circuit size increases
Solution Approach 1:
The patent uses a digital copy (register storing clock cycle count) to represent the soft start time parameter instead of using physical circuit components. The register stores a digital value that corresponds to the desired soft start time, and this digital value is used by the counter circuit to control the PWM duty cycle. This digital representation eliminates the need for multiple physical circuit configurations, thereby reducing circuit size while maintaining adjustment capability.
3Measurement precision
If a series resistance circuit with 16 resistors is used for DA conversion, then the analog signal can be divided into sixteen levels, but the circuit size increases
Solution Approach 1:
The patent replaces the mechanical/electrical system of series resistors with a digital system. Instead of using 16 physical resistors to create 16 discrete voltage levels, the invention uses a register to store a digital value representing the desired PWM duty cycle. The counter circuit then generates the appropriate PWM signal based on this digital value, eliminating the need for a large array of resistors while maintaining the ability to provide multiple discrete levels (in this case, up to 256 levels with an 8-bit register). This substitution of digital for analog components significantly reduces circuit size.
Data Source
AI summary
According to an embodiment, a DC-DC converter comprises: an error amplifier that receives a soft start signal and amplifies a difference between an output voltage signal and a reference voltage signal; a PWM control circuit that controls ON and OFF states of a first switching transistor and a second switching transistor based on the output of the error amplifier; a frequency divider that divides a frequency signal and outputting a divided frequency signal; an accumulator that performs an adding operation based on the divided frequency signal and a control signal; and a DA converter that generates the soft start signal based on an output of the accumulator.