Digital Self-Tracking Zero Current Detection for DC-DC Converters

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Solution Overview

Problem

Conventional DC-DC converters for low-power applications face efficiency degradation due to inaccurate detection of the reverse current blocking point, which requires high power consumption for accurate and rapid detection, leading to increased power consumption and efficiency issues.

Innovation Solution

A low-power DC-DC converter with a digital self-tracking zero current detection function that samples the voltage of a common contact point (VX node) using a digital sampler circuit, independent of specific reference signals, allowing for improved accuracy and reduced time to reach equilibrium, with pulse width adjustments independent of sampling intervals, enabling faster and more accurate detection of the reverse current blocking point.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fast comparator is used to detect zero current point accurately and rapidly, then measurement precision and speed are improved, but power consumption increases

Engineering Contradiction:
Improvereverse current blocking point detection accuracyVSAvoidcomparator power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces the analog comparator with a digital operation system that uses a delay circuit and digital logic to detect the reverse current blocking point. Instead of using a continuous-power-consuming analog comparator, the system uses digital sampling and timing comparison to achieve the same detection function with lower power consumption.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent employs periodic sampling of the VX node voltage at specific intervals during the switching cycle. By sampling at predetermined timing points and comparing the sampled values digitally, the system achieves accurate detection without requiring a continuously operating high-power comparator.

Inventive Principle:
Principle #19Periodic action

2Speed

If the comparator operation speed is increased to rapidly detect reverse current blocking point, then productivity is improved, but power consumption increases

Engineering Contradiction:
Improvereverse current blocking point detection speedVSAvoidcomparator power consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent pre-calculates and stores multiple delay values in a delay circuit that correspond to different detection timing points. Instead of performing complex real-time calculations, the system selectively applies pre-computed delay values to generate switching signals, achieving fast response without the power consumption of high-speed analog computation.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If delay circuit time delay is reduced to improve detection accuracy, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvereverse current blocking point detection accuracyVSAvoiddelay circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a variable delay mechanism where the delay circuit can select from multiple predetermined delay values based on operating conditions. By changing the delay parameter selectively rather than using a complex continuously-adjustable delay circuit, the system achieves accurate timing control with simpler hardware.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11095218B2Low-power DC-DC converter capable of preventing reverse current with digital operations and method of operating the same
Publication Date: 2021.08.17 ABOV SEMICON CO LTD
  • US11095218B2 patent drawing
  • US11095218B2 patent drawing
  • US11095218B2 patent drawing

AI summary

A low-power direct current-direct current (DC-DC) converter includes a capacitor, an inductor electrically connected to the capacitor, a first switch configured to be turned on for a first switching interval and supply energy from an input power source to the inductor for the first switching interval, a second switch configured to be turned on for a second switching interval and electrically connect the inductor and a ground terminal for the second switching interval, and a switching control circuit configured to generate first and second switching signals. The switching control circuit is further configured to generate a first sample signal by sampling the voltage level of a first node, and to determine, responding to the first sample signal in time domain, an pulse width adjustment adapted to adjust at least one of the length of a second switching interval and the length of a common blocking interval.