DC-DC Converter Current Emulation for Ripple Reduction
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Solution Overview
Problem
DC-DC switching regulator circuits face efficiency limitations due to noise-induced errors in reference voltage comparisons, leading to output ripple voltage and uncertainty in on-time control, especially as operating frequency increases, and the offset in current sense signals in continuous and discontinuous current modes is difficult to cancel.
Innovation Solution
A voltage converter with a control circuit that includes a sample and hold circuit to emulate load current and a comparator circuit to compare these signals, producing an enable signal to improve closed-loop voltage regulation, using a current sample and hold circuit and a 4-input comparator to enhance the accuracy of feedback and reference voltage comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If reference voltage comparison is used for PWM control, then voltage regulation is achieved, but noise-induced errors cause output ripple voltage and on-time uncertainty
Solution Approach 1:
The patent introduces a current sense signal as an intermediary measurement parameter. Instead of directly comparing reference voltage with feedback voltage, the system compares current sense signals that represent the actual current flow through the switch. This intermediary current-based measurement is less susceptible to noise and voltage ripple, thereby reducing measurement errors while maintaining regulation accuracy.
Solution Approach 2:
The patent replaces the traditional voltage-based PWM control mechanism with a current-based control mechanism. By substituting voltage comparison with current sense signal comparison, the system eliminates the harmful effects of voltage noise and ripple on measurement precision, achieving more accurate on-time control without being affected by voltage-related interference.
2Productivity
If switching frequency is increased to improve productivity, then output regulation speed improves, but reference voltage errors and output ripple increase
Solution Approach 1:
The patent substitutes voltage-based timing control with current-based timing control. The current sense signal naturally follows the switching transitions and provides a clean, noise-resistant timing reference that remains accurate at high switching frequencies. This substitution eliminates the reference voltage comparison errors that plague high-frequency operation, enabling improved productivity without sacrificing measurement precision.
3Measurement precision
If current sense circuit is added to improve measurement accuracy, then current monitoring improves, but offset cancellation becomes difficult in continuous and discontinuous modes
Solution Approach 1:
The patent extracts and separates the offset cancellation function into a dedicated circuit stage. The offset cancellation circuit is implemented as a separate module that processes the current sense signals independently, removing offset errors before the signals are used for PWM control. This extraction simplifies the overall system by providing a focused solution for offset cancellation that works consistently across both continuous and discontinuous conduction modes.
Solution Approach 2:
The patent uses a dual current sense signal approach where complementary current sense signals are generated and processed. By creating copies of the current sense measurements and processing them through matched circuit paths, the system achieves offset cancellation through differential comparison, eliminating the need for complex adaptive offset correction algorithms.
Data Source
AI summary
A voltage converter (FIG. 4) for a power supply circuit is disclosed. The voltage converter comprises a control circuit (400) coupled to receive an enable (EN) signal. The control circuit produces a first control signal (PWM) to provide a load current (IL) in response to the enable signal. A sample and hold circuit (408) is arranged to produce a third control signal (CSP) to emulate the load current and a fourth control signal (CSN′) to sample and hold value of the third control signal. A comparator circuit (416) is arranged to compare the third and fourth control signals and produce the enable signal in response to a result of the comparison.