DC-DC Converter Dead Time Compensation Using Cascaded CMOS Inverters
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Solution Overview
Problem
High-speed DC to DC switching converters face efficiency reductions due to variations in dead time delays caused by process, voltage, and temperature variations, which conventional voltage comparator circuits are unable to accurately and cost-effectively manage at high switching frequencies like 1 MHz.
Innovation Solution
The use of cascaded CMOS inverter circuits with controlled supply voltages and a MOS diode and capacitor to provide precise dead time delays, where a second CMOS inverter operates as a comparator to compensate for temperature variations and an MOS diode and capacitor address process variability, while a locally regulated supply voltage compensates for supply variations, avoiding the high cost and complexity of ultra-fast response time comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional voltage comparator circuits are used to create dead time delays, then the circuit is simple to implement, but the response time is too slow (hundreds of nanoseconds) to achieve accurate dead time control at 1 MHz switching frequencies
Solution Approach 1:
The patent extracts the comparator function from a conventional slow voltage comparator circuit and implements it using a cascaded CMOS inverter circuit. The second inverter in the cascade operates as a comparator with significantly faster response time (nanosecond range), enabling accurate dead time control at 1 MHz switching frequencies while maintaining circuit simplicity.
Solution Approach 2:
The patent changes the operating parameters of the CMOS inverter circuit to achieve fast comparator response. By configuring the second inverter with specific transistor sizing and coupling it to the regulated voltage through a MOS diode, the circuit achieves nanosecond-level response times suitable for high-frequency operation.
2Speed
If fast responding voltage comparators are used to achieve short dead time delays at high switching frequencies, then the response time is sufficient, but the cost increases significantly
Solution Approach 1:
The patent uses standard CMOS inverter circuits and common MOS components (diodes, capacitors) that are inexpensive and readily available in standard semiconductor fabrication processes. This avoids the need for specialized ultra-fast comparator ICs, significantly reducing cost while achieving the required nanosecond response times for 1 MHz operation.
3Reliability
If conventional voltage comparator circuits are used, then the circuit structure is simple, but the dead time delay varies significantly with process, voltage and temperature variations
Solution Approach 1:
The patent implements feedback through the MOS diode connection between the first inverter output and the regulated voltage node. This feedback mechanism automatically compensates for process, voltage and temperature variations by adjusting the charging current to the MOS capacitor, maintaining stable dead time delay values across varying operating conditions.
Solution Approach 2:
The patent uses parameter changes in the MOS capacitor charging process to compensate for environmental variations. The regulated voltage and MOS diode configuration adjust the charging current dynamically, maintaining consistent dead time delay despite changes in temperature, process variations, or supply voltage.
4Productivity
If increased switching frequency is used to improve converter performance, then the on-time is reduced, but the dead time delay becomes more significant relative to the on-time
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the increased significance of dead time at high frequencies through precise circuit design. The cascaded CMOS inverter configuration with MOS diode and capacitor is specifically designed to provide accurate nanosecond-level dead time control, counteracting the proportionally larger impact of dead time losses at 1 MHz operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides accurate and short dead time delay values, enhancing the efficiency and reliability of DC to DC converters across varying conditions without increasing cost or complexity, facilitating operation at high switching frequencies.
Implementation Method 1
A MOS capacitor is coupled between the first inverter output and one of the regulated voltage node and the constant voltage node... providing or establishing a first inverter delay
Implementation Method 2
a second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature.