DC-DC Converter Logic Circuit Mitigating Single Event Upsets

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Solution Overview

Problem

Existing circuits in space environments are vulnerable to disruptions caused by radiation particle hits, leading to false signals and potential catastrophic failures, particularly in DC-DC converter control logic where Triple Mode Redundancy cannot be implemented.

Innovation Solution

A logic circuit with a redundant path comprising specific logic gates (OR, NOR, AND, and DICE latches) that ensures the output remains accurate even if one of the logic gates is disrupted by an ion strike, using a multiplexer and pulldown transistor to select between internal and external clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Triple Mode Redundancy is implemented, then reliability against radiation upsets is improved, but it cannot be implemented for DC-DC converter control logic

Engineering Contradiction:
Improvereliability against radiation upsetsVSAvoidapplicability to DC-DC converter control logic
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The control logic is segmented into multiple independent logic gates (first logic gate, second logic gate) that process signals separately. Each gate receives the same input signals but processes them independently, allowing the system to detect and correct radiation-induced upsets by comparing outputs from multiple segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A latch circuit serves as an intermediary element between the logic gates and the final output. The latch stores the output state and provides a stable signal to the multiplexer, preventing transient radiation-induced errors from directly affecting the control logic output while allowing legitimate state changes to be captured and maintained.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If redundant logic paths are added, then resistance to radiation particle hits is improved, but device complexity increases

Engineering Contradiction:
Improveresistance to radiation particle hitsVSAvoidlogic circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple logic gates are merged into a unified control structure where their outputs are combined through a latch and multiplexer. This merging allows the system to achieve redundancy benefits while maintaining a compact integrated design rather than separate independent circuits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The logic circuit components serve multiple functions: the logic gates perform both normal logic operations and radiation error detection; the latch provides both state storage and error filtering; the multiplexer performs both signal selection and output control. This multi-functionality reduces overall system complexity while maintaining redundancy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If logic gates are made more robust against radiation, then reliability is improved, but the circuit becomes more complex

Engineering Contradiction:
Improverobustness against radiationVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system creates copies of the logic processing function through multiple independent logic gates that receive the same inputs. Rather than making a single gate more complex and robust, simpler copy gates are used in parallel, achieving reliability through redundancy of simple components rather than complexity of individual components.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10615799B1Circuit to mitigate single event upset perturbation in a direct current to direct current converter
Publication Date: 2020.04.07 THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY
  • US10615799B1 patent drawing
  • US10615799B1 patent drawing
  • US10615799B1 patent drawing

AI summary

A logic circuit for preventing false signals generated by radiation particle hits on sensitive nodes the circuit, comprising a first logic gate coupled to a third logic gate, a second logic gate coupled to the third logic gate, a multiplexer coupled to the third logic gate, an inverter coupled to the multiplexer, a pulldown transistor coupled to the first logic gate, and a latch coupled to the pulldown transistor. The first logic gate is coupled to the second logic gate, the pulldown transistor, and the latch. The second logic gate is coupled to the pulldown transistor and latch. The latch is coupled to the third logic gate and multiplexer. The multiplexer is coupled to the first logic gate and coupled to the second logic gate. The third logic gate outputs a high output signal only if both the first logic gate and second logic gate outputs the high output signal.