DC-DC Converter Pulse Skipping Modulation Light Load Efficiency
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Solution Overview
Problem
Conventional DC-DC converters are inefficient at low load current levels due to the high power required to switch large power field-effect transistors, and current sensing is challenging, especially with noise and circuit complexity, which negatively impacts efficiency.
Innovation Solution
A DC-DC converter using pulse skipping modulation (PSM) with an analog comparator and pulse width modulator to control output voltage within specified thresholds, eliminating the need for current sensing by measuring turn-on and turn-off times to adjust duty cycles and switch sizes based on load current levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional switched DC-DC converters use large power FETs to handle heavy loads, then high load efficiency is improved, but light load efficiency deteriorates because the power needed to switch the FETs becomes comparable or greater than the energy transferred to the load
Solution Approach 1:
The patent dynamically adjusts the size of the power FETs based on the detected load current level. At light load conditions, smaller FETs are used to reduce switching losses, while at heavy load conditions, larger FETs are activated to handle the higher current. This dynamic reconfiguration resolves the contradiction by optimizing the FET size match to the actual load requirements rather than using fixed large FETs for all conditions.
Solution Approach 2:
The invention changes the electrical parameters of the converter by detecting load current levels and adjusting the duty cycle and switching frequency accordingly. The controller modifies operating parameters such as turn-on and turn-off times of the FETs based on load conditions, enabling optimal efficiency across different load ranges without requiring current sensing hardware.
2Loss of energy
If current sensing is implemented to optimize DC-DC converter efficiency, then efficiency control is improved, but circuit complexity and noise sensitivity increase
Solution Approach 1:
The patent extracts the current sensing function from the traditional current sensing hardware approach and replaces it with a voltage-based detection method. By monitoring the output voltage and inferring load current from voltage characteristics rather than directly sensing current, the invention eliminates the need for current sensing resistors, amplifiers, and associated complex circuitry while maintaining efficiency optimization capability.
Solution Approach 2:
The invention substitutes the physical current sensing mechanism (using current sensing resistors and analog current measurement circuits) with an electrical voltage-based control system. The controller uses voltage measurements and digital processing to determine load conditions and adjust switching parameters, replacing the mechanical/electrical current sensing path with a cleaner voltage-based feedback loop that is less noisy and simpler to implement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves efficiency by reducing power losses at low load currents and optimizing switch sizes, enhancing battery life in portable devices without the need for current sensing, thereby addressing inefficiencies in conventional converters.
Implementation Method 1
an analog comparator with hysteresis adapted to control an output voltage level within a specified range, wherein as the output voltage level rises above a high threshold level, an analog comparator output becomes low and starts skipping clock pulses
Data Source
AI summary
A DC-DC converter and method of improving the efficiency of a DC-DC converter at low load current levels using pulse skipping modulation (PSM) with controllable burst duration NTclk, where Tclk is the clock cycle interval. As the average load current increases, the time between bursts decreases so that average inductor current matches the load current. The burst duration is kept around NTclk by controlling the duty cycle of the output switches. The higher the load current, the higher is the duty cycle of the output switches. No current sensing is needed. The optimum burst duration for best efficiency curve is a function of the load capacitor.