DC Fault Current Limiter Using Gate-Voltage Load Balancing
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Solution Overview
Problem
Existing DC circuit breakers face challenges in minimizing conduction losses and avoiding derating due to parallel and series connections of semiconductors, particularly in DC networks lacking natural current zero crossings.
Innovation Solution
A device utilizing a control unit to manage power semiconductor switches with varying gate-emitter voltages, employing series, anti-series, and parallel configurations of switches to balance load and minimize losses, combined with a bypass mechanism for redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power semiconductor switches are connected in series to limit fault current, then fault current limiting capability is improved, but conduction losses increase due to the series connection of multiple switches
Solution Approach 1:
The patent applies parameter changes by operating power semiconductor switches at enhanced gate-emitter voltages (e.g., +35V instead of nominal +15V) to reduce their on-state voltage drops. This parameter modification directly addresses the conduction loss issue in series-connected switches while maintaining their fault current limiting capability, thereby resolving the contradiction between reliability improvement and energy loss increase
2Power
If power semiconductor switches are connected in parallel to share current, then current carrying capacity is improved, but load balancing becomes difficult leading to derating
Solution Approach 1:
The patent uses parameter changes by applying different gate-emitter voltages to individual parallel-connected switches to actively balance their current distribution. By adjusting the gate voltage of each switch, the system achieves optimal load sharing and prevents derating, thus resolving the contradiction between improved current capacity and load balancing reliability
3Loss of energy
If enhanced gate-emitter voltage is applied to reduce conduction losses, then conduction losses decrease, but device reliability may be compromised due to increased stress on semiconductor components
Solution Approach 1:
The patent applies local quality by differentiating the gate-emitter voltage applied to each power semiconductor switch based on its specific characteristics and operating conditions. Instead of uniformly enhancing voltage across all switches, the system selectively applies enhanced voltage where needed while maintaining nominal or reduced voltage elsewhere, thereby reducing overall conduction losses without uniformly increasing stress on all components
Solution Approach 2:
The patent implements dynamics by making the gate-emitter voltage adjustable and controllable rather than fixed. The system can dynamically adapt the gate voltage levels based on real-time operating conditions, fault status, and device health, allowing optimization of conduction losses while maintaining reliability margins through flexible voltage control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low conduction losses and high reliability by balancing semiconductor loads, ensuring reliable operation even with module failures, and effectively limiting fault currents in DC networks.
Implementation Method 1
The control unit is configured to control the power semiconductor switches by means of different gate-emitter voltages. The control unit is therefore configured to switch the power semiconductor switches on or off by means of control signals
Implementation Method 2
each current limiting module comprises a plurality of power semiconductor switches and a surge arrester in a parallel connection to the power semiconductors
Data Source
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AI summary
The invention relates to a device (20) for limiting a fault current in a DC connection (21-22) with a series connection of current limiting modules (23.1-23.2n), wherein each current limiting module comprises a plurality of power semiconductor switches (331-33n) and a surge arrester (34) in parallel with the power semiconductors. The invention is characterized by a control device (26, 37) for controlling the power semiconductor switches, which is configured to control the power semiconductor switches by means of different gate-emitter voltages. The invention further relates to a method for limiting a fault current using the device.