DC Notch Filter Bandwidth Switching for MSIM Receiver Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wireless apparatuses with multiple subscriber identity modules (MSIMs) face challenges in efficiently managing hardware resources and signal interference between receiver chains, leading to glitches at the IQ output and degraded signal-to-noise ratio (SNR) and block error rate (BLER) performance.
Innovation Solution
A method is implemented to temporarily adjust the bandwidth of the direct current (DC) notch filter associated with a DC estimator in response to changes in the state of the second receiver chain, synchronizing the bandwidth changes with the slot boundaries of both receiver chains to mitigate signal interference and improve SNR/BLER performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bandwidth of the DC notch filter is increased to reduce signal interference and improve SNR/BLER performance, then the signal quality is improved, but the hardware resource usage and system complexity increase
Solution Approach 1:
The patent implements dynamic bandwidth adjustment of the DC notch filter, changing the filter bandwidth from a fixed value to a variable parameter that adapts based on receiver chain state transitions. When the second receiver chain changes state, the first DC notch filter's bandwidth is temporarily increased to mitigate interference, then returned to normal. This dynamic adjustment resolves the contradiction by providing high filter bandwidth only when needed, improving SNR/BLER performance while avoiding continuous hardware resource overhead.
Solution Approach 2:
The patent applies periodic bandwidth adjustment synchronized with slot boundaries of the receiver chains. The DC notch filter bandwidth is increased periodically at specific timing points (slot boundaries) when receiver chain state changes occur, rather than continuously. This periodic action reduces signal interference at critical moments while minimizing the duration of high hardware resource usage, thus resolving the contradiction between reliability improvement and device complexity.
2Reliability
If the bandwidth of the DC notch filter is temporarily increased to mitigate signal interference at slot boundaries, then the SNR performance is improved, but the timing synchronization complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the system monitors the state of the second receiver chain and uses this information to control the bandwidth of the first DC notch filter. When the second receiver chain changes state, this state change is detected and feeds back to trigger a temporary bandwidth increase in the first filter. This feedback-based approach simplifies timing synchronization by using the existing receiver chain state transitions as triggers, rather than requiring independent complex timing synchronization logic.
Solution Approach 2:
The patent uses the receiver chain state transitions as an intermediary to coordinate the bandwidth adjustment timing. Instead of directly implementing complex timing synchronization between slot boundaries and filter adjustments, the system uses the readily available receiver chain state changes as a mediating event that naturally aligns with slot boundaries. This intermediary approach simplifies the timing synchronization complexity while maintaining SNR performance improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces signal interference and enhances the SNR and BLER performance in wireless apparatuses operating in MSIM mode by minimizing glitches at the IQ output, optimizing hardware resource usage, and improving overall signal quality.
Implementation Method 1
temporarily increasing a first bandwidth of a direct current (DC) notch filter associated with a DC estimator of the first receiver chain
Data Source
AI summary
An apparatus is in a multi-subscriber identity module mode. A first signal in a first plurality of slots associated with a first subscription at a first receiver chain of a downlink pipe and a second signal in a second plurality of slots associated with a second subscription at a second receiver chain of the downlink pipe are received. A difference in timing of a first slot boundary of the first plurality of slots and a second slot boundary of the second plurality of slots is tracked. In response to a change of state of the second receiver chain, a first bandwidth of a direct current (DC) notch filter associated with a DC estimator of the first receiver chain is temporarily increased to a second bandwidth at a same time, prior to, or subsequent to the first slot boundary according to a timing relationship between the first and second boundaries.