Circuit and method of calibrating direct current offset in wireless communication device
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Solution Overview
Problem
Conventional DC offset calibration methods in wireless communication devices require a lengthy convergence time due to repeated adjustments of test signals, which are affected by process variations, leading to inefficient carrier leakage compensation and potential saturation of mixer circuits.
Innovation Solution
A method and circuit that estimate DC offsets using analysis formulae, generating only a few test voltage values to quickly produce a converged calibration signal, unaffected by process errors or variations, by detecting output signals and performing simple mathematical calculations to estimate and calibrate carrier leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional binary search algorithm is used to adjust DC compensation signal bits, then carrier leakage can be compensated, but calibration time becomes excessively long requiring 2.4n-4n times for n bits
Solution Approach 1:
The patent replaces the conventional binary search algorithm (iterative adjustment mechanism) with an analytical formula-based calculation method. Instead of mechanically adjusting bits through repeated testing, the system directly calculates the DC offset value using mathematical formulas involving signal power measurements, thereby eliminating the time-consuming iterative process while maintaining accurate carrier leakage compensation
Solution Approach 2:
The patent changes the calibration approach from adjusting discrete bit values through iteration to calculating continuous DC offset parameters directly. By using analytical formulas that compute the DC offset based on signal power measurements at different test conditions, the system transitions from a time-consuming search process to a direct parameter calculation, significantly reducing calibration time while maintaining compensation accuracy
2Reliability
If repeated test signals are sent into the mixer to find DC offset cancellation, then carrier leakage is compensated, but the process is affected by process variations at the transmitting end
Solution Approach 1:
The patent employs a feedback mechanism where the system measures signal power at the mixer output under different test conditions, uses these measurements to calculate the DC offset value through analytical formulas, and then applies this calculated value for compensation. This closed-loop feedback approach using mathematical modeling makes the calibration process immune to process variations, as the analytical calculation directly compensates for any variations rather than relying on iterative adjustment
3Reliability
If in-phase and quadrature branches are processed separately with binary search, then DC offset can be calibrated, but total calibration times increase to 2.4n-4n times
Solution Approach 1:
The patent replaces the iterative binary search mechanism with direct analytical calculation for both in-phase and quadrature branches. Instead of performing separate iterative adjustments for each branch, the system uses mathematical formulas to simultaneously calculate the DC offset values for both branches based on signal power measurements, thereby eliminating the cumulative time cost of separate binary search processes and significantly improving calibration efficiency
Data Source
AI summary
A circuit for calibrating the DC offset in a wireless communication device utilizes a voltage-generating circuit to generate a first voltage value and its negative value, and utilizes a detecting circuit to detect an output of the wireless communication device and generate a first target-branch reference value corresponding to the power of the output when the first voltage value is inputted into a target branch (e.g., the in-phase branch or the quadrature branch) of the wireless communication device, and detect an output of the wireless communication device and generate a second target-branch reference value corresponding to the power of the output when the negative value of the first voltage value is input into the target branch. Then, an estimating circuit estimates the DC offset on the target branch according to the first and second target-branch reference values and the first voltage value.