Differential DC Offset Cancellation Circuit for Low Cutoff Frequency
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Solution Overview
Problem
Direct conversion receivers face challenges with DC offset elimination, particularly in achieving low cutoff frequencies for high signal quality while maintaining a small-sized integrated circuit implementation and reducing settling time.
Innovation Solution
A DC offset elimination device with a first and second signal path, utilizing an operational transconductance amplifier (OTA) with a bias circuit, transconducting circuits, and a capacitor pair to deliver and feedback differential signal pairs, allowing for low cutoff frequencies and shortened settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resistance of the resistor network and capacitance of the capacitor pair are increased to lower the cutoff frequency, then the quality of the output signal pair is improved, but the area of the integrated circuit increases and parasitic capacitance increases
Solution Approach 1:
The patent changes the electrical parameters of the transconductor (specifically the transconductance value) to achieve the desired cutoff frequency without requiring large physical components. By adjusting the transconductance parameter g_m1, the circuit can achieve low cutoff frequencies while maintaining a compact integrated circuit implementation.
2Measurement precision
If the resistance of the resistor network and capacitance of the capacitor pair are increased to lower the cutoff frequency, then the quality of the output signal pair is improved, but parasitic capacitance increases
Solution Approach 1:
The patent uses parameter changes in the transconductor's transconductance to achieve low cutoff frequency without relying on large passive components that would introduce parasitic capacitance. This approach maintains signal quality while minimizing harmful parasitic effects.
3Loss of time
If the cutoff frequency is increased to reduce the settling time, then the settling time is shortened, but the quality of the output signal pair deteriorates
Solution Approach 1:
The patent dynamically adjusts the transconductance parameter of the transconductor to achieve fast settling time without compromising signal quality. By controlling the transconductance value, the circuit can quickly eliminate DC offset while maintaining the low cutoff frequency needed for high signal quality.
Data Source
AI summary
A DC offset elimination device includes a first signal path that delivers a differential input signal pair from an input node to an output node and a second signal path that delivers a differential output signal pair from the output node to the input node. The second signal path includes a first transconductor having an input terminal coupled to the output node, an amplifier having an input terminal coupled to an output terminal of the first transconductor, a capacitor coupled in parallel to the amplifier, and a second transconductor coupled to the output terminal of the amplifier and to the input node.