DC Offset Calibration Circuit With Low Flicker Noise

The patent changes the operating parameters of the transistors by biasing them in the triode region rather than saturation region, and uses polysilicon resistors instead of standard resistors. This parameter change allows the transistors to operate with lower noise while maintaining the resolution benefits of smaller device sizes.

The patent employs a composite structure combining polysilicon resistors with transistors operating in the triode region. This composite approach leverages the low noise characteristics of polysilicon resistors together with the controlled resistance properties of triode-region transistors to achieve both high resolution and low flicker noise.

The patent implements a feedback mechanism where the operational amplifier continuously monitors and compensates for DC offset at its inputs. The feedback path includes the polysilicon resistors and triode-region transistors that generate compensation currents to cancel the DC offset, allowing high gain operation without DC offset degradation.

The patent applies preliminary anti-action by pre-establishing compensation currents through the switched current sources before the DC offset fully develops. The calibration circuit proactively generates opposing currents to counteract the expected DC offset, preventing it from degrading the receiver performance.