DC Offset Compensation Circuit for Short-Preamble RF Receivers
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Solution Overview
Problem
Conventional RF receiver chips face challenges in accurately estimating and compensating for DC offsets within short time frames, particularly in high-data rate communication schemes like 802.11a/g/n, where the existing DC offset adjustment circuits are insufficient due to limited time for estimation.
Innovation Solution
A DC offset adjustment method and apparatus that utilize a filter to estimate DC offsets based on digital samples within a sample period equal to the signal's periodic period, incorporating a low pass filter to smooth the estimate and remove high-frequency artifacts, allowing for effective DC offset compensation even in zero-mean periodic signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DC offset adjustment circuit with feedback loop and weighting factor is used, then DC offset can be estimated and removed, but the estimation requires sufficient time (150-200 microseconds) which is not available in short preamble schemes (8 microseconds)
Solution Approach 1:
The patent extracts only the periodic component of the signal for DC offset estimation by using a correlator that correlates the received signal with a locally generated periodic signal. This extraction allows the estimator to focus solely on the periodic portion, enabling accurate DC offset estimation within the short 8-microsecond preamble window without requiring the full 150-200 microseconds of conventional methods.
Solution Approach 2:
The patent performs preliminary action by pre-generating the periodic signal template and preparing the correlation structure before the actual DC offset estimation is needed. The correlator is pre-configured with the expected periodic waveform, allowing immediate processing of the incoming signal during the short preamble period, thus enabling fast convergence without requiring extended observation time.
2Reliability
If DC offset compensation is performed using conventional methods, then residual DC offset can be reduced, but the method fails to converge quickly enough for high-data rate schemes with short preambles
Solution Approach 1:
The patent implements feedback by using the output of the correlator to directly adjust the DC offset compensation value. The correlator continuously monitors the periodic component and provides real-time feedback on the DC offset level, allowing the system to dynamically adjust and maintain accurate compensation throughout the short preamble period, ensuring reliability even at high data rates.
Solution Approach 2:
The patent leverages the periodic nature of the signal by using a correlator that specifically targets and processes only the periodic components. By synchronizing the estimation process with the signal's periodicity, the system achieves rapid convergence within each period, enabling effective DC offset compensation for high-data rate schemes where the entire preamble duration is only 8 microseconds.
3Device complexity
If a simple averaging estimator is used, then the circuit complexity is reduced, but the estimator cannot accurately track DC offset in signals with carrier frequency offset
Solution Approach 1:
The patent introduces an intermediary element - the correlator - that acts as a mediator between the received signal and the DC offset estimator. The correlator processes the signal to extract the periodic component and remove the effects of carrier frequency offset before passing the cleaned signal to the simple averaging estimator. This intermediary allows the use of a low-complexity estimator while maintaining high accuracy in the presence of frequency offsets.
Data Source
AI summary
An apparatus has front end circuitry to demodulate a radio frequency signal and to produce a baseband signal, the radio frequency signal being periodic and having a predetermined period. An analog-to-digital converter converts the baseband signal into a digital signal, the digital signal being periodic and having the predetermined period. A DC offset adjustment circuit includes a filter for estimating a DC offset contained in the digital signal based only on digital samples in a sample period having a length equal to the predetermined period. An adder removes the estimated DC offset from the digital signal. A method of operating such an apparatus is also disclosed.