DCAP Cell Architecture for DRC Compliance and On-Chip Decoupling
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Solution Overview
Problem
The existing use of FILL cells in integrated circuit design leads to waste of valuable chip real estate and is not entirely satisfactory, as they lack functionality and are used to connect power and ground rails as well as solve design rule violations.
Innovation Solution
The introduction of decoupling capacitor (DCAP) cells, which are process-friendly and can be formed using M0 and M1 metal layers or PMOS transistors, to solve design rule checking violations and provide decoupling capacitance, thereby reducing noise and maintaining stable voltage levels without requiring additional M0 and M1 layer resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FILL cells are used to connect power and ground rails and solve design rule violations, then design rule violations are resolved, but valuable chip real estate is wasted due to the lack of functionality in FILL cells
Solution Approach 1:
The patent applies multi-functionality by designing FILL cells that simultaneously serve two purposes: (1) maintaining design rule compliance by connecting power and ground rails, and (2) providing decoupling capacitance to reduce noise and stabilize voltage. This transforms previously non-functional FILL cells into multi-functional elements that contribute to both structural compliance and electrical performance, thereby eliminating the waste of chip real estate while resolving design rule violations
2Reliability
If additional decoupling capacitance is provided to reduce noise and maintain stable voltage levels, then power supply stability is improved, but additional M0 and M1 layer resources are required
Solution Approach 1:
The patent integrates decoupling capacitance functionality directly into the FILL cells, which are already present in the layout for design rule compliance. By incorporating capacitive elements (such as metal plates connected to power and ground rails) within the existing FILL cell structure, the solution provides additional decoupling capacitance without requiring separate dedicated capacitor structures or additional M0 and M1 layer resources beyond what is already allocated for the FILL cells
Solution Approach 2:
The patent merges the decoupling capacitance function with the FILL cell structure by combining two previously separate functions (design rule compliance and noise reduction) into a single integrated element. The FILL cell now contains both the structural elements needed for design rule compliance and the capacitive elements needed for power supply stabilization, eliminating the need for separate implementations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DCAP cells effectively address design rule checking violations and provide decoupling capacitance, reducing noise and maintaining stable voltage levels while conserving M0 and M1 layer resources, thus optimizing chip layout and functionality.
Implementation Method 1
the one or more DCAP cells comprise at least one capacitor formed by an M0 metal layer and an M1 metal layer
Data Source
AI summary
Methods and Apparatuses for making an integrated circuit (IC) are disclosed. In accordance with some embodiments, a method including forming one or more decoupling capacitor (DCAP) cells comprising one or more polysilicon (PO) layers openings formed based on one or more photoresist layer openings formed to solve one or more design rule check (DRC) violations. The one or more DCAP cells also provide decoupling capacitors for the IC.