Duty-Cycle Corrected Clock Multiplication for Low-Jitter PLLs
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Solution Overview
Problem
Integrated circuits face limitations in clock signal generation, including high PLL jitter, power dissipation, and excessive voltage-controlled oscillator (VCO) gain, which are not effectively addressed by conventional clocking systems.
Innovation Solution
The implementation of duty-cycle corrected multiply-by-two (×2) circuitry, combined with clock gating cell (CGC) circuits and strategic placement of duty cycle correction (DCC) circuits, reduces power consumption and VCO gain, allowing for lower jitter and more efficient clock signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If low reference clock signals are used to reduce BOM costs, then cost is reduced, but PLL jitter increases
Solution Approach 1:
The clock multiplication function is segmented from the PLL into a separate duty cycle corrected x2 circuit. This allows the PLL to operate at lower frequencies with reduced jitter while the separate circuit handles frequency multiplication, resolving the contradiction between low reference clock cost and PLL jitter performance.
Solution Approach 2:
A duty cycle corrected x2 circuit is introduced as an intermediary between the PLL output and the final clock signal. This intermediary circuit multiplies the frequency by 2 while correcting duty cycle, enabling the PLL to use lower frequency reference clocks without increasing jitter, thus reducing BOM cost while maintaining reliability.
2Device complexity
If conventional clock distribution is used, then simplicity is maintained, but power dissipation increases
Solution Approach 1:
The clock distribution network is segmented into multiple independent duty cycle corrected x2 circuits distributed throughout the integrated circuit. Each circuit serves a local region, reducing the power dissipation of the global clock distribution network while maintaining operational simplicity through standardized modular units.
3Speed
If high frequency clock gating is implemented, then speed is improved, but power consumption increases due to tight setup times
Solution Approach 1:
The mechanical clock gating operation at high frequency is replaced by duty cycle corrected x2 circuits that operate at lower frequencies. This substitution allows clock gating to achieve the required speed performance while consuming less power, as the tight setup time constraints are eliminated by operating at reduced frequencies.
4Device complexity
If conventional PLL arrangements are used, then clock signal generation is simplified, but VCO gain becomes excessive
Solution Approach 1:
The frequency multiplication function is extracted from the VCO and implemented in separate duty cycle corrected x2 circuits. This extraction reduces the VCO gain to appropriate levels while maintaining simplified clock signal generation through modular, standardized circuit units.
Data Source
AI summary
A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (DCC) circuit portion, and a clock gating circuit portion. The multiplier circuit portion, DCC circuit portion, and clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit. Additionally, the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency.