DCDC Converter Clock Division to Protect Radio Reception Sensitivity
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Solution Overview
Problem
Radio communication devices face increased power consumption without sufficient reduction, leading to degraded reception sensitivity due to harmonic components from switching operations in DCDC converters, particularly in applications like smart meters with strict sensitivity requirements.
Innovation Solution
Incorporating a variable frequency divider and a DCDC converter that synchronizes switching operations with a frequency divided clock, ensuring that integral multiples of the frequency used for voltage generation do not fall within the high-frequency signal band, thereby preventing interference and maintaining sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a DCDC converter is used to reduce power consumption, then power consumption is reduced, but reception sensitivity is degraded due to harmonic components from switching operations
Solution Approach 1:
The patent changes the frequency parameter of the switching operation by using a frequency divider to divide the reference clock frequency before providing it to the DCDC converter. This frequency transformation ensures that harmonic components of the switching operation do not fall within the reception frequency band, thereby resolving the contradiction between power consumption reduction and reception sensitivity maintenance
Solution Approach 2:
The patent introduces a frequency divider as an intermediary component between the reference clock and the DCDC converter. This intermediary transforms the clock frequency to an appropriate value that enables the DCDC converter to operate with reduced power consumption while preventing harmful harmonic interference in the reception band
2Productivity
If switching frequency is increased to improve voltage generation efficiency, then power consumption is reduced, but harmful harmonic components are generated in the high-frequency signal band
Solution Approach 1:
The patent transforms the switching frequency parameter by dividing the reference clock frequency using a frequency divider. This parameter change allows the system to operate at an optimized switching frequency that maintains voltage generation efficiency while shifting harmonic components away from the harmful high-frequency signal band
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses power consumption increases while preserving reception sensitivity, even in applications with stringent sensitivity constraints, by controlling the frequency dividing ratio to exclude interfering frequencies, thus enhancing the device's performance.
Implementation Method 1
a DCDC converter that performs a switching operation in synchronization with the frequency divided clock to output an output voltage obtained by stepping down an input voltage
Data Source
AI summary
According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.