DCDC Switching Clock Control to Protect Radio Reception Sensitivity

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Solution Overview

Problem

Radio communication devices face increased power consumption without sufficient reduction, leading to degraded reception sensitivity due to harmonic components from switching operations in DCDC converters, particularly in applications like smart meters with stringent sensitivity requirements.

Innovation Solution

Incorporating a variable frequency divider and a DCDC converter that performs switching operations in synchronization with a frequency divided clock, controlled to avoid integral multiples of the frequency divided clock within the high-frequency signal band, thereby suppressing power consumption and preventing sensitivity degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a DCDC converter is used to reduce power consumption, then power consumption is reduced, but reception sensitivity is degraded due to harmonic components from switching operations

Engineering Contradiction:
Improvepower consumptionVSAvoidreception sensitivity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the frequency parameter of the switching operation by using a frequency divided clock instead of the original reference clock. The frequency dividing ratio is adjusted so that the switching frequency and its harmonics fall outside the radio reception frequency band, thereby resolving the contradiction between power consumption reduction and reception sensitivity maintenance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic adjustment of the frequency dividing ratio based on the radio reception frequency band. The controller dynamically selects different dividing ratios to ensure that switching harmonics never overlap with the reception band, allowing the system to adapt to different operating conditions while maintaining both low power consumption and high reception sensitivity

Inventive Principle:
Principle #15Dynamics

2Productivity

If switching operation frequency is increased to improve efficiency, then conversion efficiency is improved, but harmonic components interfere with radio reception

Engineering Contradiction:
Improveconversion efficiencyVSAvoidharmonic interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful harmonic components from the radio reception band by carefully selecting the frequency dividing ratio. This ensures that switching harmonics are separated from the reception frequency band, allowing high switching frequency for efficiency without causing interference to radio reception

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces power consumption while maintaining reception sensitivity by ensuring that high-frequency components do not interfere with radio reception, particularly in applications with severe sensitivity restrictions.

Implementation Method 1

a DCDC converter that performs a switching operation in synchronization with the frequency divided clock to generate an output voltage obtained by stepping down an input voltage

Methodology Applied
Scientific EffectSwitching operation:

Implementation Method 2

a variable frequency divider that divides a frequency of a reference clock and outputs a frequency divided clock

Methodology Applied
Scientific EffectFrequency division:

Data Source

PatentUS9832724B2Radio communication device and radio communication method
Publication Date: 2017.11.28 RENESAS ELECTRONICS CORP
  • US9832724B2 patent drawing
  • US9832724B2 patent drawing
  • US9832724B2 patent drawing

AI summary

According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.