DC/DC Converter Control Circuit for High Duty Cycle Operation
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Solution Overview
Problem
DC/DC converters face limitations in achieving high duty cycles due to conduction disoverlap time constraints, particularly when operating conditions vary, leading to inefficient power management and limited maximum achievable duty cycles.
Innovation Solution
A control circuit arrangement that operates in two modes based on duty cycle conditions, using a feedback network for moderate duty cycles and bypassing it for high duty cycles to ensure optimal disoverlap time and prevent simultaneous transistor conduction, utilizing a phase generator and clock control circuit to generate gate signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a feedback network is provided to recognize transistor off-state before switching on the other transistor, then simultaneous transistor conduction is prevented, but the maximum duty cycle is limited due to disoverlap time requirements
Solution Approach 1:
The patent implements a dynamic control mechanism where the disoverlap time is adjusted based on the operating duty cycle. For high duty cycle operations (above threshold), the feedback network is bypassed and a fixed shorter disoverlap time is applied. For moderate duty cycles, the feedback network operates with a longer disoverlap time. This dynamic adaptation resolves the contradiction by optimizing the disoverlap time parameter according to operating conditions, thereby maximizing duty cycle while maintaining reliability.
2Reliability
If a minimum off-time is fixed for driver transistors to reset analog parts, then proper reset operations are ensured, but the complementary driver stays off longer than necessary reducing efficiency
Solution Approach 1:
The patent changes the parameter of disoverlap time based on operating conditions. By implementing two different disoverlap time values (first disoverlap time for high duty cycle, second longer disoverlap time for moderate duty cycle), the system optimizes the balance between ensuring proper analog part reset and minimizing unnecessary off-time. This parameter adaptation resolves the contradiction by providing sufficient reset time only when necessary.
3Productivity
If the frequency of the pulse-width modulated signal is increased to provide maximum duty cycle, then power management efficiency improves, but the disoverlap time constraints become more severe
Solution Approach 1:
The patent implements dynamic adjustment of disoverlap time based on the duty cycle parameter. When operating at high frequencies with maximum duty cycle requirements, the system switches to the first disoverlap time value which is optimized for high-frequency operation. This dynamic parameter adaptation allows the system to maintain high productivity while managing the disoverlap time constraints effectively.
Data Source
AI summary
A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.