DC-DC Converter Out-of-Audio Circuit for PFM Noise Control
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Solution Overview
Problem
Switch mode regulators operating in pulse frequency modulation (PFM) mode often reduce switching frequency to the audio range, causing audible noise due to insufficient control over frequency and duty cycle variations.
Innovation Solution
A DC-DC regulator system incorporating an out-of-audio circuit that compares the converter clock signal to a minimum threshold frequency, using a counter and digital-to-analog converter to regulate current through NFETs, ensuring operation above audio frequencies and maintaining a wide separation between control and out-of-audio bandwidths to prevent audible noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the regulator is operated in PFM mode to reduce output voltage when load current drops below minimum threshold, then the output voltage regulation is improved, but the switching frequency is reduced to audio frequency range causing audible noise
Solution Approach 1:
An out-of-audio circuit is introduced as an intermediary component between the PFM controller and the power circuit. This circuit includes a frequency comparison circuit that compares the actual switching frequency with a minimum threshold frequency, and a counter that generates a compensation current signal when the frequency drops into the audio range. The compensation current is injected into the output node to prevent the frequency from falling below the audible threshold, thereby eliminating audible noise while maintaining voltage regulation capability.
Solution Approach 2:
The out-of-audio circuit implements a feedback mechanism by continuously monitoring the switching frequency through the frequency comparison circuit and adjusting the compensation current accordingly. When the frequency drops below the minimum threshold, the counter increments and generates a compensation current that feeds back to the output node, effectively preventing further frequency reduction and audible noise generation. This closed-loop feedback ensures the switching frequency remains above the audible range while maintaining proper voltage regulation.
2Power
If the switching frequency is reduced to increase current supplied to the load in PFM mode, then the power delivery capability is improved, but the regulator emits audible noise
Solution Approach 1:
The out-of-audio circuit acts as an intermediary that mediates between the power delivery requirement and the audible noise constraint. It monitors the switching frequency and, when it approaches the audible range, generates a compensation current that prevents further frequency reduction. This allows the system to deliver adequate current to the load while maintaining the switching frequency above the audible threshold, thus eliminating audible noise without sacrificing power delivery capability.
Solution Approach 2:
The system dynamically adjusts the compensation current parameter based on the switching frequency. When the frequency drops into the audio range, the counter generates a compensation current that effectively increases the total current available to the load. This parameter change (adding compensation current) allows the system to maintain power delivery capability while preventing frequency reduction that would cause audible noise.
Data Source
AI summary
A DC-DC regulator system includes a power circuit which has a first input coupled to receive an input voltage, a second input coupled to receive a control signal and an output to provide a regulated output voltage. The system includes a control circuit which has a first input coupled to receive the regulated output voltage, a second input coupled to receive a reference voltage, a first output to provide the control signal, and a second output to provide a converter clock signal. The system includes an out-of-audio circuit which has a first input coupled to receive a minimum threshold frequency signal, a second input coupled to receive the converter clock signal, a third input coupled to the power circuit output, and a fourth input coupled to receive a bandwidth control clock signal.