DC-DC Converter Period Control for Low-Load Ripple Stability
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Solution Overview
Problem
Existing DC-DC converters face challenges in maintaining power efficiency and generating a stable output voltage at low load conditions, often resulting in voltage ripple due to attempts to reduce power consumption.
Innovation Solution
A DC-DC converter design that includes a smoothing filter, switching elements, and control circuits for dynamic voltage detection and period determination, allowing for efficient power management by adjusting the charging period of the inductor based on detected voltage limits, without relying on high-speed clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power consumption is reduced at low load, then energy efficiency improves, but output voltage stability deteriorates due to ripple
Solution Approach 1:
The patent implements dynamic switching between two control modes: PFM (Pulse Frequency Modulation) for low load conditions and CCM (Continuous Conduction Mode) for high load conditions. The control circuit dynamically adjusts the operating mode based on load requirements, enabling the converter to achieve low power consumption at light loads while maintaining output voltage stability through appropriate mode selection.
Solution Approach 2:
The patent changes the operating parameters of the DC-DC converter by adjusting the switching frequency and conduction mode based on load conditions. At low load, the converter operates in PFM mode with lower switching frequency to reduce power consumption, while at high load, it transitions to CCM mode to maintain voltage stability, thus adapting parameters to resolve the contradiction between power consumption and voltage stability.
2Loss of energy
If switching frequency is reduced to improve power efficiency, then energy loss decreases, but ripple voltage increases
Solution Approach 1:
The patent employs periodic switching action in PFM mode where the switching frequency is dynamically adjusted based on the output voltage level. The converter switches periodically at optimized frequencies that balance power efficiency and ripple suppression, using the natural periodic charging and discharging of the inductor to maintain voltage stability while minimizing energy loss.
Solution Approach 2:
The control circuit incorporates feedback mechanisms that monitor the output voltage and adjust the switching frequency accordingly. When ripple voltage increases, the feedback control adjusts the switching parameters to reduce ripple while maintaining power efficiency. This closed-loop feedback ensures that the converter automatically optimizes the trade-off between switching frequency, power efficiency, and ripple voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved power efficiency and stable output voltage at low load conditions, reducing ripple and enabling the converter to be used in place of low dropout regulators, thereby minimizing circuit size and transition time.
Implementation Method 1
a smoothing filter including an inductor L1 and a first capacitive element C1 and configured to smooth an output voltage VO of an external output terminal
Implementation Method 2
a smoothing filter including an inductor L1 and a first capacitive element C1 and configured to smooth an output voltage VO
Data Source
AI summary
A DC-DC converter is disclosed. The DC-DC converter includes a first switching element between an external input terminal and an inductor of a smoothing filter, a second switching element provided between the inductor and a reference voltage terminal, a control circuit for on-off controlling the first and second switching elements according to the upper and lower limit values of the output voltage, and a period determination circuit configured to determine the predetermined period based on the voltage corresponding to the upper limit value of the output voltage.