DC/DC Converter Switching Control With Adaptive Dead Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing switching devices and DC/DC converters face inefficiencies due to simultaneous turning-on of high-side and low-side transistors, particularly in varying load conditions, where traditional methods either diminish efficiency or struggle to optimize performance across different operational modes.
Innovation Solution
The implementation of a switching IC with adjustable delay times for transistor control, utilizing delay setting and adding circuits to optimize dead times based on edge timing differences, ensuring efficient operation across heavy and light load conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed dead time is used to prevent simultaneous turning-on of transistors, then reliability is improved, but efficiency deteriorates under varying load conditions
Solution Approach 1:
The patent implements dynamic dead time adjustment by detecting the actual turn-on timing of transistors and adjusting the dead time period accordingly. The control circuit varies the dead time based on operating conditions, transforming a static parameter into a dynamic one that adapts to different load situations, thereby reducing switching losses while maintaining reliable operation.
Solution Approach 2:
The patent changes the dead time parameter from a fixed value to a variable value that adjusts based on actual transistor switching timing and load conditions. By modifying this critical timing parameter dynamically, the system optimizes the balance between preventing simultaneous conduction (reliability) and minimizing dead time losses (efficiency).
2Reliability
If dead time is extended to ensure proper transistor switching, then reliability is improved, but productivity deteriorates due to reduced switching frequency
Solution Approach 1:
The patent employs feedback mechanisms where the control circuit detects the actual turn-on timing of transistors and uses this information to adjust subsequent dead time periods. This closed-loop approach ensures that the dead time is sufficient for reliable switching while being minimized to maintain high switching frequency, thereby resolving the contradiction between reliability and productivity.
Solution Approach 2:
By making the dead time period dynamic rather than fixed, the system can adapt the switching timing to actual operating conditions. This allows the system to maintain reliable transistor switching control while optimizing the switching frequency for maximum productivity under different load conditions.
3Device complexity
If traditional fixed delay control is used, then device complexity is reduced, but adaptability deteriorates under different operational modes
Solution Approach 1:
The patent implements a self-adjusting control system where the control circuit automatically detects transistor switching timing and adjusts dead time parameters without external intervention. This self-service mechanism provides adaptability across different operational modes while maintaining relatively simple device architecture, as the system adjusts itself based on real-time feedback.
Solution Approach 2:
The feedback-based automatic adjustment mechanism enables the control circuit to adapt to different load conditions and operational modes. By continuously monitoring switching timing and adjusting dead time accordingly, the system achieves high adaptability without significantly increasing device complexity, as the same control circuit performs both monitoring and adjustment functions.
Data Source
AI summary
A first transistor and a second transistor disposed on the lower-potential side of the first transistor are connected in series with each other. Based on a level change in a drive control signal, the first transistor is turned on at the lapse of a first delay time and the second transistor is turned off at the lapse of a second delay time. Based on the gate signals to the first and second transistors, the turn-on timing of the first transistor and the turn-off timing of the second transistor are sensed. Based on the difference between those timings, at least one of the first and second delay times is changed to reduce a dead time.