DCDL Delay Estimation for Fast DLL Locking With Fewer TDC Stages
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Solution Overview
Problem
Conventional delay locked loops (DLLs) require a large number of time-to-digital converter (TDC) stages to achieve large delay resolution, leading to increased layout area and power consumption, as well as reduced linearity, especially in high-speed applications.
Innovation Solution
A delay estimation device comprising a pulse generator, a digitally controlled delay line (DCDL), a TDC, and a control circuit that operates in a fast lock mode by generating multiple clock signals and phase signals based on delay line codes, allowing for efficient delay estimation with fewer TDC stages, reducing layout area and power consumption while maintaining linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL increases delay from minimum to desired value, then delay accuracy is improved, but locking time increases significantly
Solution Approach 1:
The patent applies preliminary action by using a time-to-digital converter (TDC) to pre-measure the timing difference between input clock signal and delayed clock signal before the main delay locking process. This preliminary measurement provides initial timing information that guides the DLL to start from a closer delay point, significantly reducing the number of cycles needed to achieve lock while maintaining accurate delay measurement.
2Loss of time
If TDC stages are increased to reduce lock time, then locking speed is improved, but layout area and power consumption increase
Solution Approach 1:
The patent segments the delay measurement function into two parts: a coarse measurement performed by a TDC that provides timing information, and a fine measurement performed by the DLL delay line. This segmentation allows the system to achieve fast locking without requiring a large number of TDC stages, as the TDC provides sufficient initial guidance and the DLL completes the precise adjustment with fewer stages needed.
3Measurement precision
If more TDC stages are used for large delay resolution, then delay measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by using the TDC to perform only the coarse timing measurement rather than the complete high-precision delay measurement. The TDC provides sufficient timing information to guide the DLL, and the DLL completes the precise adjustment. This partial use of TDC stages achieves the required delay resolution without the excessive power consumption that would result from using many TDC stages for the entire measurement range.
4Measurement precision
If delay line circuit is expanded for timing comparison, then timing measurement range is improved, but device complexity increases
Solution Approach 1:
The patent merges the timing comparison function into the existing DLL delay line structure. The TDC provides timing information that controls the delay line, and the same delay line circuit performs both the delay function and the timing comparison function. This merging eliminates the need for a separate delay line circuit dedicated to timing comparison, reducing device complexity while maintaining the required timing measurement range.
Data Source
AI summary
The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.