DCDL Delay Estimation for Fast-Locking DLL Timing
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Solution Overview
Problem
Conventional delay locked loops (DLLs) require a large number of time-to-digital converter (TDC) stages to achieve large delay resolution, leading to increased layout area and power consumption, as well as reduced linearity, especially in high-speed applications.
Innovation Solution
A delay estimation device comprising a pulse generator, a digitally controlled delay line (DCDL), a TDC, and a control circuit that operates in a fast lock mode to reduce the number of TDC stages needed by using a combination of delay line codes to estimate the specific delay from a reference delay time, thereby improving locking efficiency and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL increases/counts delay from minimum to desired value, then delay resolution is achieved, but locking time becomes very long
Solution Approach 1:
The patent applies preliminary action by using a time-to-digital converter (TDC) to pre-measure the timing difference between first and second rising edges before the main delay locking process. This preliminary measurement provides an initial estimate of the desired delay, allowing the DLL to jump closer to the target delay value and significantly reducing the number of counting cycles needed to achieve lock.
2Loss of time
If TDC stages are increased to reduce lock time, then timing measurement capability is improved, but layout area and power consumption increase
Solution Approach 1:
The patent makes the delay line circuit multi-functional by using it for both delay generation in the DLL and timing measurement in the TDC. The same delay elements are reused for dual purposes: providing programmable delay values and serving as the measurement medium for timing difference detection. This eliminates the need for a separate dedicated measurement circuit, reducing overall layout area while maintaining fast locking capability.
3Measurement precision
If TDC stages are increased to achieve large delay resolution, then timing precision is improved, but linearity deteriorates
Solution Approach 1:
The patent introduces a digital code conversion and lookup table mechanism as an intermediary between the TDC measurement and the delay line control. The TDC outputs a digital timing code that is converted through a lookup table or algorithm to determine the appropriate delay line code. This intermediary processing stage linearizes the relationship between timing difference and delay value, compensating for non-linearities that would otherwise accumulate with multiple TDC stages.
Data Source
AI summary
The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.