DCDL Delay Estimation with Lookup-Based Fast DLL Locking
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Solution Overview
Problem
Conventional delay locked loops (DLLs) require a large number of time-to-digital converter (TDC) stages for large delay times, leading to increased layout area and power consumption, as well as reduced linearity, especially in high-speed applications.
Innovation Solution
A delay estimation device comprising a pulse generator, a digitally controlled delay line (DCDL), a TDC, and a control circuit that operates in a fast lock mode by generating clock signals and phase signals based on delay line codes, allowing for efficient delay estimation with fewer TDC stages, reducing layout area and power consumption while maintaining linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL increases/counts delay from minimum to desired value, then delay estimation is achieved, but locking time becomes very long for large delay times
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay time information in a lookup table before the actual delay estimation process. When delay estimation is needed, the system directly retrieves the pre-computed values instead of counting from minimum to desired value, significantly reducing locking time while maintaining estimation accuracy.
2Loss of time
If TDC is used to reduce lock time by measuring timing difference, then locking speed improves, but the number of TDC stages must increase for large delay times
Solution Approach 1:
The patent uses a lookup table that stores pre-computed delay time information as a copy of the delay characteristics. Instead of physically extending the TDC chain to cover large delay ranges, the system copies the delay information into a digital table that can be quickly searched and retrieved, reducing both hardware complexity and lock time.
3Measurement precision
If more TDC stages are added to handle large delay times, then delay detection range increases, but layout area and power consumption increase significantly
Solution Approach 1:
The patent replaces the physical extension of the TDC delay line (mechanical approach) with a digital lookup table system. Instead of adding more delay stages to extend the detection range, the system uses a memory-based approach where delay characteristics are stored and retrieved digitally, dramatically reducing layout area while maintaining or extending the effective delay detection range.
4Measurement precision
If more TDC stages are added to handle large delay times, then delay detection range increases, but power consumption increases
Solution Approach 1:
The patent substitutes the power-hungry physical delay line extension with a low-power digital lookup table implementation. The memory-based storage and retrieval of delay information consumes significantly less power than driving additional TDC delay stages, especially for high-speed applications where many stages would be required to cover large delay ranges.
5Measurement precision
If conventional DLL uses many TDC stages for large delay times, then delay detection capability improves, but linearity deteriorates
Solution Approach 1:
The patent copies the ideal delay characteristics into a lookup table, preserving the linear relationship between delay control words and actual delay times. By retrieving pre-computed values from memory rather than physically passing signals through many cascaded delay stages, the system maintains linearity even for large delay ranges where physical TDC chains would exhibit non-linear behavior.
Data Source
AI summary
The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.