Digitally Controlled Delay Line Gain Calibration for Spur Reduction
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Solution Overview
Problem
Digitally controlled delay lines (DCDLs) in phase-locked loops (PLLs) suffer from gain errors that cause fractional spurious signals, which are challenging to filter out without affecting the desired output.
Innovation Solution
A two-step calibration process is employed to calibrate the gain of the DCDL by suspending the PLL operation, using the time-to-digital converter as a phase detector and the frequency synthesizer as an infinite-range digital-to-time converter to adjust the DCDL gain, setting a reference delay, and matching it to the full scale code value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If DCDL gain is not calibrated, then the device complexity is lower and operation is simpler, but fractional spurious signals appear in the PLL output
Solution Approach 1:
The system uses its own existing components (time-to-digital converter and frequency synthesizer) to perform the calibration function, rather than introducing external calibration equipment. The TDC acts as a phase detector and the frequency synthesizer as a digital-to-time converter, allowing the system to self-calibrate the DCDL gain without adding significant external complexity.
Solution Approach 2:
Existing components are made multi-functional: the time-to-digital converter serves both its normal timing function and as a phase detector for calibration; the frequency synthesizer serves both signal generation and as a digital-to-time converter for providing calibration signals. This reduces overall system complexity by reusing existing hardware for multiple purposes.
2Measurement precision
If DCDL gain is calibrated using traditional methods, then measurement precision improves, but the calibration process becomes more complex and time-consuming
Solution Approach 1:
The calibration system uses the PLL's own internal components (TDC and frequency synthesizer) to perform gain calibration, eliminating the need for external precision measurement equipment. This achieves accurate calibration while keeping the calibration process integrated within the existing system architecture.
Solution Approach 2:
The system performs gain calibration as a preliminary step before normal operation or at scheduled intervals. By suspending normal PLL operation temporarily to perform calibration, the system ensures accurate gain settings are established beforehand, improving measurement precision without requiring complex continuous calibration mechanisms.
3Measurement precision
If continuous calibration is performed, then gain accuracy is maintained, but productivity decreases due to suspended PLL operation
Solution Approach 1:
Instead of continuous calibration, the system performs calibration periodically or at scheduled intervals (e.g., during initialization, after power-on, or at predetermined time intervals). This maintains gain accuracy over time while minimizing the impact on PLL productivity, as the PLL operates normally between calibration events.
Solution Approach 2:
The system performs gain calibration as a preliminary action during initialization or setup phases before entering normal operation. By completing calibration beforehand, the system ensures accurate gain settings are established without requiring repeated suspensions during productive operation, thus maintaining both accuracy and productivity.
Data Source
AI summary
A system to operate as a phase locked loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. A retimer subsystem is arranged to receive the output of the frequency synthesizer. A digitally controlled delay line (DCDL) is arranged to receive an output of the retimer. A phase detector is arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicating a difference in phase of the output of the delay line relative to the output of the DCDL. A controller causes closed loop operation of the PLL during a normal operational mode and open loop operation during a calibration mode during which gain of the DCDL, defining a relationship between a control code and a resulting delay, is calibrated.