DCDL Gain Calibration Using Error Injection in PLLs
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Solution Overview
Problem
Phase-locked loop (PLL) circuits using digitally controlled delay lines (DCDLs) face challenges such as phase noise, spurs, non-linear characteristics, and gain errors, which affect signal quality and operation, particularly in high-frequency applications like clock clean-up circuits and wireless communication links.
Innovation Solution
Incorporating error injection circuits to intentionally introduce delay signals, reducing phase differences by calibrating the DCDL using first and second error injection circuits controlled by digital logic, which adjusts delays based on pseudorandom binary sequences to mitigate gain errors and improve signal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digitally controlled delay line is used in a phase-locked loop, then the phase control range is improved, but gain errors and non-linear characteristics are introduced
Solution Approach 1:
The patent implements a feedback mechanism where the output of the digitally controlled delay line is fed back to its input through a phase detector. The phase detector compares the delayed output signal with the input signal and generates an error signal that is used to adjust the delay line's control signal. This closed-loop feedback system automatically compensates for gain errors and non-linear characteristics by continuously correcting the delay based on the actual phase difference measurement, thereby resolving the contradiction between extended phase control range and measurement precision.
Solution Approach 2:
The delay line calibration circuit performs self-calibration by using its own output signal as the reference for comparison. The circuit automatically adjusts its own control parameters through the feedback mechanism without requiring external calibration equipment or manual intervention. This self-service approach enables the system to autonomously compensate for its own gain errors and non-linearities, maintaining measurement precision while utilizing the full phase control range.
2Measurement precision
If error injection circuits are added to calibrate the delay line, then gain errors are reduced, but device complexity increases
Solution Approach 1:
The patent merges the calibration function with the existing phase-locked loop structure by integrating the error injection circuits into the feedback path. The calibration process uses the same phase detector and control signal lines already present in the PLL, combining multiple functions (phase detection, error detection, and calibration) into a unified circuit architecture. This merging approach reduces the need for separate calibration equipment and minimizes overall device complexity while achieving gain error reduction.
Solution Approach 2:
The phase detector and control signal lines are designed to serve multiple functions: normal phase detection during operation and calibration during initialization or maintenance modes. The error injection circuits utilize the existing feedback path and control mechanisms of the PLL, making the calibration system multi-functional rather than requiring dedicated separate circuits. This universality reduces device complexity by reusing existing components for dual purposes.
Data Source
AI summary
The techniques described herein relate to digitally controlled delay line gain calibration using error injection. An example apparatus includes a digitally controlled delay line (DCDL) with a DCDL output and configured to: receive a clock signal to be output from a voltage-controlled oscillator, and delay the clock signal to generate a first delayed clock signal. The apparatus further includes an error injection circuit with a first error injection input and a second error injection input, the first error injection input coupled to the DCDL output. The apparatus additionally includes a phase controller with a phase controller output coupled to the second error injection input, the phase controller configured to, in response to a pseudorandom binary sequence signal, instruct the error injection circuit to generate a second delayed clock signal based on a delay of the first delayed clock signal.