DCDL Gain Calibration in PLLs for Fractional Spur Reduction
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Solution Overview
Problem
Digitally controlled delay lines (DCDLs) in phase-locked loops (PLLs) suffer from gain errors, leading to fractional spurious signals that are difficult to filter out, affecting the desired output in applications like digital PLL-based frequency synthesizers.
Innovation Solution
A two-step calibration process is implemented where the PLL is operated in a closed loop during normal mode and switched to open loop for calibration, using a reference delay line to adjust the DCDL, allowing for precise calibration of the DCDL gain without affecting the PLL's feedback path, thereby reducing fractional spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gain calibration of DCDL is performed in closed-loop mode, then calibration can be done continuously, but calibration accuracy is reduced due to feedback interference
Solution Approach 1:
The patent implements periodic calibration by switching the PLL between closed-loop normal operation and open-loop calibration mode at predetermined intervals. During calibration periods, the PLL operates in open-loop mode to allow accurate DCDL gain calibration, then returns to closed-loop mode for normal operation. This periodic switching enables accurate calibration without continuous feedback interference while maintaining overall system functionality.
Solution Approach 2:
The patent performs preliminary calibration actions by adjusting the DCDL gain before normal PLL operation begins or after completing calibration cycles. The controller pre-calibrates the DCDL by adjusting its gain based on measured delay values, ensuring accurate delay control is established before the PLL enters closed-loop operation. This preliminary calibration prevents feedback interference during the calibration process.
2Productivity
If DCDL gain is not calibrated, then PLL operates continuously in closed loop, but fractional spurious signals appear in the output
Solution Approach 1:
The patent uses feedback mechanisms to detect and correct DCDL gain errors. The phase detector measures phase differences between signals, and the controller uses this feedback information to adjust the DCDL gain during calibration modes. This feedback-driven calibration process eliminates fractional spurious signals by ensuring accurate delay control while allowing the PLL to operate continuously in closed-loop mode between calibration cycles.
Solution Approach 2:
The patent implements periodic calibration cycles where the PLL temporarily switches to open-loop mode to calibrate DCDL gain, then returns to closed-loop operation. This periodic calibration prevents fractional spurious signals from appearing in the output by regularly correcting DCDL gain errors, while minimizing disruption to continuous PLL operation. The calibration occurs at predetermined intervals to maintain signal quality.
3Measurement precision
If calibration is performed by taking PLL offline, then DCDL can be calibrated accurately, but output signal is lost during calibration
Solution Approach 1:
The patent implements periodic calibration where the PLL switches to open-loop mode at predetermined intervals to perform accurate DCDL calibration, then returns to closed-loop mode for normal operation. This periodic approach allows precise calibration to be performed periodically without continuously interrupting signal output, minimizing the loss of signal availability while maintaining calibration accuracy.
Solution Approach 2:
The patent performs preliminary calibration actions during brief open-loop intervals before returning to closed-loop operation. The controller quickly adjusts the DCDL gain based on measured delay values during these brief calibration windows, then resumes normal signal generation. This preliminary calibration approach maintains output signal availability by completing calibration tasks during brief intervals rather than extended offline periods.
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
A system to operate as a phase locked loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. A retimer subsystem is arranged to receive the output of the frequency synthesizer. A digitally controlled delay line (DCDL) is arranged to receive an output of the retimer. A phase detector is arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicating a difference in phase of the output of the delay line relative to the output of the DCDL. A controller causes closed loop operation of the PLL during a normal operational mode and open loop operation during a calibration mode during which gain of the DCDL, defining a relationship between a control code and a resulting delay, is calibrated.