DCDL-MDLL Frequency Multiplier for Low-Power Phase Rotation

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Solution Overview

Problem

Existing phase interpolators (PI) face challenges in generating high-frequency multi-phase clock signals efficiently, leading to high power consumption and hardware area requirements, as well as issues with linearity correction.

Innovation Solution

A frequency multiplier for phase rotation is introduced, comprising a digitally controlled delay line (DCDL) and a multiplying delay-locked loop (MDLL), along with a DCDL calibration circuit to adjust the gain and achieve infinite phase shift.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a phase interpolator uses a multi-phase clock signal having substantially the same frequency as the output signal to generate high-frequency clock signals, then the output frequency is improved, but power consumption and hardware area increase significantly

Engineering Contradiction:

Improveoutput clock frequencyVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent changes the frequency parameter of the input clock signal by using a frequency divider to generate a lower frequency clock signal, which is then processed by the phase interpolator. This allows the phase interpolator to operate at lower frequencies while still achieving high-frequency output through the frequency multiplication effect, thereby reducing power consumption while maintaining high output frequency capability

Inventive Principle:

Principle #35Parameter changes

2Speed

Engineering Contradiction:

Improveoutput clock frequencyVSAvoidhardware area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent changes the frequency parameter by using a frequency divider to generate a lower frequency clock signal for the phase interpolator. This parameter change allows the use of a simpler, smaller-scale phase interpolator design that requires less hardware area while still achieving the desired high-frequency output through the interaction with the frequency multiplier circuit

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If a phase interpolator is used to generate multi-phase clock signals, then phase adjustment capability is improved, but linearity correction requires additional power consumption

Engineering Contradiction:

Improvephase adjustment capabilityVSAvoidpower consumption for linearity correction

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces a feedback mechanism where the output of the phase interpolator is fed back to control the frequency divider. This feedback loop enables automatic linearity correction by adjusting the division ratio based on the actual output phase, thereby maintaining phase accuracy without requiring additional power-consuming correction circuits

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12348233B2Frequency multiplier for phase rotation

Publication Date: 2025.07.01 SAMSUNG ELECTRONICS CO LTD

AI summary

A frequency multiplier includes a first digitally controlled delay line (DCDL) configured to receive a first clock signal and generate a second clock signal by changing a phase of the first clock signal, a multiplying delay-locked loop (MDLL) configured to generate a third clock signal by multiplying a frequency of the second clock signal, and a DCDL calibration circuit configured to receive the second clock signal and generate a gain signal for adjusting a gain of the first DCDL where a difference between a maximum delay and a minimum delay of the first DCDL is substantially equal to a period of the third clock signal.