DCI Joint Delay Encoding for Downlink Scheduling Feedback

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Solution Overview

Problem

Existing wireless communication systems face inefficiencies in signaling for acknowledgment feedback delay and downlink scheduling delay, particularly due to insufficient bits for indicating possible acknowledgment feedback delays and separate indications increasing signaling overhead.

Innovation Solution

Jointly encoding downlink shared channel scheduling delay and acknowledgment feedback delay within a single DCI field, allowing the UE to determine these delays using configurable bits or a table, thereby reducing signaling overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate indications are used for downlink scheduling delay and acknowledgment feedback delay, then each delay can be indicated independently, but signaling overhead increases

Engineering Contradiction:
Improveindependent delay indicationVSAvoidsignaling overhead
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent combines separate downlink scheduling delay and acknowledgment feedback delay indications into a single unified indication field in DCI. This merging reduces the total number of bits required for signaling while still allowing the UE to determine both delay values, thereby reducing signaling overhead while maintaining the capability to indicate both delays.

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If insufficient bits are allocated for acknowledgment feedback delay indication, then signaling overhead is reduced, but the range of possible delays that can be indicated is limited

Engineering Contradiction:
Improvesignaling overheadVSAvoiddelay indication range
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The unified indication field serves multiple functions: it can indicate downlink scheduling delay, acknowledgment feedback delay, or combinations thereof. By making the indication field universal and multi-functional, the system can cover a broader range of delay values and scenarios without requiring separate dedicated fields for each delay type, thus expanding the indication range while keeping signaling overhead low.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a configurable parameter dimension where the UE and base station can agree on specific mappings between indication values and delay combinations. This additional configurational dimension allows the system to expand the effective delay indication range beyond what a fixed bit allocation would permit, enabling flexible adaptation to different network conditions and requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP4342114B1Flexible signaling for acknowledgment feedback delay and downlink scheduling delay
Publication Date: 2026.02.04 QUALCOMM INC
  • EP4342114B1 patent drawingFigure 1
  • EP4342114B1 patent drawingFigure 2
  • EP4342114B1 patent drawingFigure 3

AI summary

Methods, systems, and devices for wireless communications are described. A downlink shared channel scheduling delay and an acknowledgment feedback delay may be jointly encoded and sent to a user equipment (UE). For example, a downlink control information (DCI) field may jointly indicate the downlink shared channel scheduling delay and the acknowledgment feedback delay in a field of 'X' bits, where 'X' is configurable by a base station (e.g., via radio resource control (RRC) signaling). Subsequently, the UE may then determine the downlink shared channel scheduling delay and the acknowledgment feedback delay from the DCI by using respective equations based on a value from the jointly encoded indication or by using a table based on the value from the jointly encoded indication. Additionally, the downlink shared channel scheduling delay and the acknowledgment feedback delay may be expressed in terms of absolute subframes, invalid/valid subframes, or both.