Frozen-Bit Matrix Recovery of DCI Scrambling Seed Bits
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Solution Overview
Problem
Current techniques for multi-UE testing consume excessive computing and networking resources due to unnecessary decoding operations and exhaustive searches for scrambling sequence initialization vectors in downlink signals, particularly in scenarios where the RNTI or initialization vector is unknown.
Innovation Solution
A method involving the construction of a frozen decode matrix and a linear feedback shift register (LFSR) generator matrix to generate a mapping matrix, which allows recovery of the scrambling sequence seed bits without descrambling operations or exhaustive searches, utilizing the mapping matrix to initialize the scrambler and perform actions based on the recovered seed bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-UE testing techniques are used with exhaustive searches for scrambling sequence initialization vectors, then comprehensive testing coverage is achieved, but excessive computing and networking resources are consumed
Solution Approach 1:
The patent extracts and utilizes frozen bits from the downlink control information that are already present in the transmitted signal. These frozen bits contain embedded information about the scrambling sequence initialization vector, allowing the system to retrieve this information directly without performing exhaustive searches or additional decoding operations on the entire signal.
Solution Approach 2:
The system performs preliminary extraction and processing of frozen bits from the downlink control information before attempting to recover the scrambling sequence initialization vector. This preliminary action identifies the initialization vector information early in the processing chain, avoiding the need for resource-intensive exhaustive searches later in the testing process.
2Measurement precision
If exhaustive searches are performed to find scrambling sequence initialization vectors, then accurate recovery is achieved, but significant time and computational resources are wasted
Solution Approach 1:
The patent extracts initialization vector information directly from the frozen bits that are already embedded in the transmitted downlink control information. This extraction method provides accurate recovery of the initialization vector without requiring time-consuming exhaustive searches through multiple candidate vectors.
Solution Approach 2:
The frozen bits serve as an intermediary that carries information about the scrambling sequence initialization vector. By using these intermediate frozen bits as a mediator, the system can recover the initialization vector accurately and efficiently, avoiding direct exhaustive search methods.
3Reliability
If full decoding operations are performed on downlink signals with unknown RNTI or initialization vector, then complete signal processing is achieved, but unnecessary computing resources are consumed
Solution Approach 1:
The patent extracts only the necessary frozen bits from the downlink control information that contain initialization vector information, rather than performing complete decoding operations on the entire signal. This selective extraction maintains processing completeness for the critical parameters while significantly improving efficiency by avoiding unnecessary processing of other signal components.
Solution Approach 2:
The system performs partial decoding operations focused specifically on extracting frozen bits containing initialization vector information, rather than performing excessive full decoding operations on the entire downlink signal. This partial action approach achieves the necessary processing completeness while improving overall productivity.
Data Source
AI summary
A device may receive a downlink signal from a base station and may construct a frozen decode matrix for decoding frozen bits from data of the downlink signal. The device may construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits and may multiply the frozen decode matrix and the LFSR generator matrix to generate a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits. The device may determine an inverse matrix of the mapping matrix and may multiply the inverse matrix and the frozen decode matrix to obtain a final matrix. The device may utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits used to initialize the component and may perform actions based on the scrambling sequence seed bits.