Flexible DCIM Bank Addressing to Reduce Memory Data Duplication
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Solution Overview
Problem
Existing memory systems suffer from degraded storage density and CIM utilization ratio due to data duplication across memory banks caused by shared row addresses, leading to inefficiencies in accessing and reading operations.
Innovation Solution
Implement flexible bank addressing by providing different row addresses and read-enable signals for individual or subset groups of memory banks, allowing selective access and minimizing data duplication during IF shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared row addresses are used for memory banks, then device complexity is reduced, but storage density and CIM utilization ratio are degraded due to data duplication
Solution Approach 1:
The patent segments the memory bank addressing into two levels: shared row addresses for common access and unique column addresses for bank-specific access. This segmentation allows different memory banks to be addressed independently through column address differentiation while maintaining simplified row address sharing, thereby reducing data duplication and improving storage density without significantly increasing overall addressing complexity
Solution Approach 2:
The patent applies local quality by providing unique column addresses to individual memory banks or groups of memory banks while maintaining shared row addresses for common access. This allows specific memory banks to have differentiated addressing characteristics tailored to their local needs, enabling flexible access patterns that reduce data duplication in specific regions without affecting the entire memory array
2Device complexity
If shared row addresses are used for memory banks, then device complexity is reduced, but CIM utilization ratio is degraded due to data duplication during IF shifts
Solution Approach 1:
The patent implements dynamic addressing by allowing flexible selection of row addresses for different memory banks during IF shifts. The system can dynamically change which memory banks are accessed based on the current computational needs, enabling efficient data flow patterns that improve CIM utilization ratio without requiring complex static addressing configurations
Solution Approach 2:
The patent performs preliminary actions by pre-configuring unique column addresses for memory banks and establishing the flexible bank addressing structure before computational operations begin. This preliminary setup enables efficient data access patterns during IF shifts without requiring complex real-time address generation, thereby improving CIM utilization while maintaining manageable system complexity
3Quantity of substance
If different row addresses are provided for individual memory banks, then data duplication is reduced and storage density is improved, but device complexity increases
Solution Approach 1:
The patent segments the addressing structure into shared row addresses and unique column addresses, where column addresses provide bank-specific differentiation. This segmentation enables individual memory banks to have unique addressing identifiers without requiring completely separate address spaces, thereby improving storage density while limiting the increase in overall addressing complexity to only the column address portion
4Productivity
If flexible bank addressing is implemented, then array efficiency and power efficiency are improved, but device complexity increases due to additional multiplexers and control signals
Solution Approach 1:
The patent makes the column address inputs universal by using them for multiple purposes: bank selection, row address differentiation, and data path routing. This multi-functionality reduces the need for separate dedicated control signals for each function, thereby improving array efficiency and power efficiency while limiting the increase in addressing control complexity to essential multiplexer and signal additions
Data Source
AI summary
A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply-accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply-accumulate operation using the second portion and the third portion.