Flexible DCIM Bank Group Addressing for Higher CIM Utilization

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Solution Overview

Problem

Existing memory systems suffer from degraded storage density and CIM utilization ratio due to data duplication across memory banks caused by common row addresses, leading to inefficiencies in accessing and reading operations.

Innovation Solution

Implement flexible bank addressing by providing different row addresses and read-enable signals for individual or subset groups of memory banks, allowing selective access and minimizing data duplication during IF shifts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If common row addresses are used for all memory banks, then address input requirements are reduced, but data duplication occurs across memory banks degrading storage density and CIM utilization ratio

Engineering Contradiction:
Improveaddress input requirementsVSAvoidstorage density
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent segments memory banks into different groups (first bank groups and second bank groups) with independent row address inputs. This segmentation allows each group to have its own address control, eliminating the need for all memory banks to share common row addresses, thereby preventing data duplication while maintaining manageable address input requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different row address inputs are provided for different memory bank groups, allowing each group to be addressed independently with its own row address. This local quality approach enables flexible addressing where each memory bank group can be accessed without forcing data duplication across all banks, thus improving storage density while keeping address inputs organized by group.

Inventive Principle:
Principle #3Local quality

2Device complexity

If common row addresses are used for all memory banks, then addressing structure is simplified, but CIM utilization ratio is degraded due to data duplication

Engineering Contradiction:
Improveaddressing structureVSAvoidCIM utilization ratio
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Memory banks are segmented into multiple groups with independent row address inputs. This segmentation enables the system to maintain a relatively simple addressing structure at the group level while achieving high CIM utilization ratio at the individual bank level by avoiding data duplication through independent addressing of each group.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic row address selection where different row addresses can be provided to different memory bank groups based on operational needs. This dynamic addressing allows the system to optimize CIM utilization ratio by selectively accessing specific bank groups without requiring complex global addressing for all banks simultaneously.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If different row addresses are provided for different memory bank groups, then data duplication is minimized improving storage density, but address input complexity increases

Engineering Contradiction:
Improvestorage densityVSAvoidaddress input complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By segmenting memory banks into groups with independent row address inputs, the system minimizes data duplication and improves storage density. The complexity is managed through segmentation rather than providing completely independent addressing for each individual bank, as group-level addressing reduces the overall number of address inputs required.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple memory bank groups share common column address inputs while having independent row address inputs. This universality approach allows the system to achieve high storage density through different row addressing while reducing overall address input complexity by reusing column address lines across groups, making the addressing structure more efficient.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of operation

If data is duplicated across memory banks for common row addresses, then reading operations can access any bank, but unnecessary data switches occur reducing array efficiency

Engineering Contradiction:
Improvereading operation flexibilityVSAvoidarray efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

Memory banks are segmented into groups with independent row addresses, allowing reading operations to target specific groups without requiring data duplication across all banks. This segmentation maintains reading operation flexibility within each group while eliminating unnecessary data switches between groups, thereby improving array efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the row address control function at the group level rather than at the individual bank level. This extraction allows the system to maintain reading flexibility for each memory bank group while avoiding the data duplication and unnecessary switches that would occur with common row addresses across all banks, thus improving overall array efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250349329A1Systems and methods for flexible bank addressing in digital computing-in-memory (DCIM)
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250349329A1 patent drawing
  • US20250349329A1 patent drawing
  • US20250349329A1 patent drawing

AI summary

A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply—accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply—accumulate operation using the second portion and the third portion.