Duty Cycle Adjuster Setting with DCM Offset Boundaries
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a semiconductor device's mode register, allowing for precise adjustment of internal clock duty cycles through programmable DCA codes and multiple step sizes, and identification of DCM offsets to optimize clock timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjustment is not sufficiently accurate without precise setting
Solution Approach 1:
The patent implements a feedback mechanism where the memory device measures its own duty cycle distortion and communicates the magnitude and direction of distortion to the memory controller. The controller then adjusts the DCA setting accordingly, creating a closed-loop system that automatically achieves accurate duty cycle correction without requiring complex manual calibration procedures.
Solution Approach 2:
The memory device performs self-diagnosis by measuring its internal clock duty cycle distortion and reporting the results to the controller. This self-service capability eliminates the need for external testing equipment or complex setup procedures, allowing the system to automatically identify and correct duty cycle issues through the DCA adjustment mechanism.
2Manufacturing precision
If multiple DCA settings are tested to find optimal duty cycle adjustment, then accurate duty cycle is achieved, but time consumption increases
Solution Approach 1:
The system performs preliminary duty cycle measurement and characterization during manufacturing or initialization, storing the measured distortion parameters for later use. This preliminary action allows the system to skip extensive trial-and-error adjustment during operation, as the optimal DCA setting can be directly determined from the pre-measured distortion characteristics.
Solution Approach 2:
The patent implements a feedback mechanism where the memory device measures its own duty cycle distortion and communicates the magnitude and direction of distortion to the memory controller. The controller then adjusts the DCA setting accordingly, creating a closed-loop system that automatically achieves accurate duty cycle correction without requiring complex manual calibration procedures.
3Measurement precision
If duty cycle monitoring and adjustment features are added to mode register, then precise clock timing control is enabled, but device complexity increases
Solution Approach 1:
The patent integrates the duty cycle adjuster control within the existing mode register structure, which is a standard component for memory device configuration. By reusing the established mode register interface and encoding the DCA settings using existing opcode formats, the system achieves multi-functional capability (duty cycle adjustment, timing control, and configuration) without adding separate complex control mechanisms.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.