DCNN Hardware Accelerator SoC for Mobile Power Efficiency
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Solution Overview
Problem
Deep convolutional neural networks (DCNNs) require significant computational resources and power, making them unsuitable for mobile devices due to their large size and high bandwidth, power, and computing resource demands, which limits their deployment in everyday life, especially in mobile and wearable devices.
Innovation Solution
A hardware accelerator engine is developed, incorporating a system on chip (SoC) with digital signal processor clusters, a reconfigurable dataflow accelerator fabric, and convolution accelerators to efficiently process DCNN operations, reducing power consumption and memory traffic while maintaining high throughput, enabling real-time computer vision applications in embedded devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DCNN is implemented on conventional hardware platforms, then computational accuracy is improved, but power consumption and device size increase significantly
Solution Approach 1:
The DCNN architecture is segmented into distinct functional blocks (convolutional layers, pooling layers, fully connected layers) that can be independently optimized and executed. This segmentation allows the system to process data in manageable chunks, reducing overall power consumption while maintaining computational accuracy through specialized hardware acceleration for each layer type.
Solution Approach 2:
The system dynamically adjusts computational parameters such as precision levels, activation functions, and network depth based on available power resources and performance requirements. By changing these parameters adaptively, the system maintains acceptable computational accuracy while significantly reducing power consumption on mobile devices.
2Adaptability or versatility
If DCNN architecture is deepened to improve learning capability, then model performance is improved, but bandwidth and memory requirements increase
Solution Approach 1:
The patent implements a hierarchical memory architecture where frequently accessed weights and activations are stored in fast on-chip memory, while less frequently accessed data resides in slower off-chip memory. This nested memory structure allows deep DCNN models to operate with reduced bandwidth requirements by keeping critical data in fast memory, thereby supporting deeper architectures without proportionally increasing memory demands.
Solution Approach 2:
The system transforms the computational approach by introducing temporal dimension through batch processing and spatial dimension through parallel convolution operations. This multi-dimensional processing allows the system to handle deep network architectures efficiently by distributing computational load across multiple dimensions, reducing peak memory bandwidth requirements.
3Productivity
If DCNN is deployed in mobile devices to improve application functionality, then computational throughput is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal DCNN accelerator core that can execute multiple DCNN architectures (e.g., AlexNet, VGG, ResNet) and support various convolution operations through configurable parameters. This multi-functional design achieves high computational throughput for different applications without requiring separate dedicated hardware for each model, thereby controlling device complexity while maintaining versatility.
4Ease of operation
If conventional DCNN implementation is used to maintain simplicity, then ease of operation is improved, but computational resources and processing time increase
Solution Approach 1:
The system performs preliminary actions by pre-computing and storing convolution kernels, activation functions, and other computational elements in on-chip memory before actual inference. This preprocessing allows the DCNN to execute rapidly during runtime without requiring complex real-time computations, thereby reducing processing time while keeping the implementation relatively simple through hardware acceleration.
Data Source
AI summary
Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.