DCO Multi-Rate DEM With Adaptive Mismatch Noise Cancellation

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Solution Overview

Problem

Digital fractional-N phase locked loops (PLLs) face challenges in reducing phase error due to frequency control element (FCE) mismatches, which cause nonlinear distortion and increase phase noise, especially in applications requiring low phase noise like cellular telephone transceivers, where existing solutions either require high power consumption or are impractical.

Innovation Solution

A digital fractional-N PLL with multi-rate dynamic element matching (DEM) and adaptive mismatch-noise cancellation (MNC) is implemented, using a phase error to digital converter and a digital loop filter to suppress quantization noise and drive a digitally controlled oscillator (DCO) with both integer and fractional banks of FCEs, where MNC logic estimates and updates coefficient values to minimize FCE mismatch errors during normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If digital fractional-N PLL is used instead of analog PLL, then circuit area is reduced and compatibility with scaled CMOS technology is improved, but phase error performance deteriorates due to FCE mismatches

Engineering Contradiction:
Improvecircuit areaVSAvoidphase error performance
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent implements adaptive mismatch-noise cancellation that continuously monitors and corrects FCE mismatch errors in real-time during normal PLL operation. The system estimates ideal MNC coefficient values through feedback from the PLL's phase error signal, then applies corrections to minimize the impact of FCE mismatches on phase noise performance.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces mismatch-noise cancellation logic as an intermediary component between the FCEs and the PLL feedback path. This intermediary estimates and cancels the noise generated by FCE mismatches before it degrades the phase error performance, effectively mediating between the digital architecture and the analog performance requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If offline calibration technique is used to address FCE mismatches, then manufacturing precision is improved, but productivity deteriorates due to several minutes calibration time

Engineering Contradiction:
ImproveFCE mismatch calibration accuracyVSAvoidcalibration time
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent performs mismatch calibration actions preliminarily by estimating ideal MNC coefficient values during normal PLL operation rather than requiring a separate offline calibration phase. The system proactively continuously adapts to FCE mismatch conditions, eliminating the need for time-consuming pre-calibration while maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous mismatch cancellation during normal PLL operation rather than performing calibration as a discrete preliminary step. The adaptive MNC logic continuously estimates and corrects FCE mismatch errors, ensuring uninterrupted useful action without periods of degraded performance during calibration.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If DCO input signal changes frequently, then adaptability is improved, but phase noise performance deteriorates due to spectral breathing from FCE mismatches

Engineering Contradiction:
ImproveDCO frequency tuning rangeVSAvoidphase noise performance
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic mismatch cancellation that adapts in real-time as the DCO input signal changes. The MNC logic continuously estimates ideal coefficient values based on current operating conditions, allowing the system to maintain phase noise performance across the full frequency tuning range without spectral breathing effects.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the MNC coefficient parameters dynamically in response to DCO frequency changes. By estimating and updating coefficient values during normal operation, the system adapts to different operating points and maintains optimal phase noise performance across varying frequency conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10735005B2Multi-rate DEM with mismatch noise cancellation for digitally-controlled oscillators
Publication Date: 2020.08.04 RGT UNIV OF CALIFORNIA
  • US10735005B2 patent drawing
  • US10735005B2 patent drawing
  • US10735005B2 patent drawing

AI summary

A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.