Digitally Controlled Oscillator Frequency Locking Without Drift
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Solution Overview
Problem
Existing frequency-locking loops in electronic devices, such as USB interfaces, face challenges with drift and prolonged locking times due to the high frequency clock being linked to a low frequency reference clock, particularly evident in the use of crystal oscillators which are expensive and prone to instability.
Innovation Solution
A digitally controlled oscillator (DCO) configuration that eliminates division operations and uses a variable-modulus-fixed-increment approach, allowing for rapid locking of high frequency clocks to low frequency clocks without drift, utilizing a fixed oscillator frequency greater than the output frequency and adjusting the modulus based on the ratio of oscillator cycles to achieve precise frequency locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop with low-pass filter is used to lock 48 MHz clock to 1 KHz reference, then frequency locking is achieved, but drift occurs between input and output clocks due to limited filter response capability
Solution Approach 1:
The patent replaces the traditional analog phase-locked loop with a digitally controlled oscillator system. The DCO uses digital counting and modulus adjustment mechanisms instead of analog filters and voltage-controlled oscillation, eliminating the drift issue caused by limited low-pass filter response capability while maintaining frequency locking accuracy.
Solution Approach 2:
The patent implements dynamic modulus adjustment in the frequency-locking loop. The modulus value is continuously adapted based on the ratio of oscillator cycles to reference cycles, allowing the system to maintain accurate frequency locking without the drift problems of fixed-parameter analog systems.
2Reliability
If a traditional phase-locked loop is used with 48,000:1 frequency ratio, then frequency locking is achieved, but locking time is prolonged due to multiple cycles required before lock
Solution Approach 1:
The patent performs preliminary calculation of the modulus value based on the known frequency ratio before the locking process begins. By pre-determining the appropriate modulus setting, the system eliminates the prolonged locking time required by traditional PLLs to converge through multiple cycles, achieving rapid frequency acquisition.
Solution Approach 2:
The patent uses a fixed oscillator frequency that is a whole number multiple of the output frequency, creating a simplified integer relationship. This copying approach with integer ratios eliminates the complex convergence requirements of traditional PLLs, enabling rapid locking without prolonged adjustment periods.
3Measurement precision
If a 48 MHz crystal oscillator is used to provide the clock signal, then precise frequency is achieved, but cost increases due to expensive crystal component
Solution Approach 1:
The patent replaces the expensive 48 MHz crystal oscillator with a digitally controlled oscillator using a fixed oscillator and digital modulus adjustment mechanism. This substitution uses cheaper electronic components while maintaining the required frequency precision through digital control, significantly reducing manufacturing cost.
Solution Approach 2:
The patent changes the fundamental operating parameter from fixed crystal frequency to dynamically adjustable digital oscillator frequency. By controlling the modulus parameter digitally, the system achieves the required 48 MHz precision without relying on expensive crystal components, enabling cost-effective frequency generation.
Data Source
AI summary
A digitally controlled oscillator (DCO) that generates an output frequency clock signal without drift and can be rapidly locked to an input or reference clock is described. A variable-modulus-fixed-increment form of DCO is configured to divide the frequency of a nominally fixed frequency oscillator. A constant is derived from the ratio of a fixed increment to the desired output frequency; this constant is multiplied by the frequency of the oscillator and the modulus adjusted to keep the ratio of the input clock and the output clock constant. The frequency of the oscillator is conveniently measured by counting the number of cycles between input cycles of a reference frequency. The oscillator must be greater in frequency than the expected output and is most accurate in cases where the reference frequency is low compared to the expected output frequency.