DCO Gain Normalization in Locked Loops for Fast PLL Locking
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Solution Overview
Problem
Digital phase-locked loops face challenges in compensating for digitally-controlled oscillator (DCO) gain variations due to process, voltage, and temperature (PVT) variations, leading to errors in frequency and phase output signals.
Innovation Solution
A method and system for DCO gain normalization, which involves determining a scaling factor to adjust loop filter gain constants, using calibration codewords and state machine hardware to map measured DCO gain to nominal gain, thereby minimizing PVT-induced errors and achieving ultra-fast locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DCO circuits are used with digital-to-analog frequency mapping, then the circuit structure remains simple, but DCO gain variation occurs under PVT variations causing frequency and phase errors
Solution Approach 1:
The patent changes the operational parameters of the DCO by applying a scaling factor to the control word input based on measured DCO gain. This parameter adjustment compensates for PVT variations without requiring fundamental circuit redesign, thereby improving frequency accuracy while maintaining relative structural simplicity
Solution Approach 2:
The patent implements a feedback mechanism where the actual DCO gain is measured and used to calculate a scaling factor that adjusts subsequent control words. This closed-loop feedback compensates for gain variations dynamically, improving reliability without significantly increasing circuit complexity
2Productivity
If traditional PLL locking methods are used, then the locking process is straightforward, but the lock time exceeds hundreds of reference clock cycles
Solution Approach 1:
The patent performs preliminary measurement of the DCO gain and calculation of the scaling factor before the PLL locking process begins. This preliminary action characterizes the DCO behavior in advance, enabling faster convergence during locking and reducing the overall lock time to less than 30 reference clock cycles
Solution Approach 2:
The patent dynamically adjusts the DCO control words using the pre-calculated scaling factor during the locking process. This dynamic adaptation allows the PLL to converge faster by compensating for gain variations in real-time, significantly improving locking speed
Data Source
AI summary
A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.