DCO Gain Normalization in Digital PLLs Under PVT Variation
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Solution Overview
Problem
Conventional digital phase-locked loops face challenges in compensating for gain variations in digitally-controlled oscillators (DCOs) due to process, voltage, and temperature (PVT) variations, leading to errors in frequency and phase output signals.
Innovation Solution
A locked-loop circuit that includes a time-to-digital converter, digital loop filter, and digitally-controlled oscillator (DCO) with calibration logic to determine a scaling factor, normalizing the DCO codeword gain and applying it to the output bits, thereby compensating for PVT-induced gain variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DCO circuits generate periodic output based on multi-bit DCO codeword under PVT variations, then the circuit structure remains simple, but gain variation occurs causing error in frequency and phase output
Solution Approach 1:
The patent applies preliminary action by performing calibration of the DCO gain at manufacturing time or initialization. A calibration circuit determines the actual DCO codeword gain under various PVT conditions and stores calibration data. This pre-characterization allows the system to compensate for gain variations without adding complex real-time adjustment circuits, thereby improving output signal accuracy while maintaining relatively simple circuit structure.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the DCO control word based on calibrated gain information. The system changes the effective DCO gain parameter through digital control word modification rather than hardware changes. By multiplying the control word by a gain compensation factor derived from calibration, the system compensates for PVT-induced gain variations, improving reliability without significantly increasing device complexity.
2Measurement precision
If DCO gain variation is compensated through calibration, then output signal accuracy improves, but PLL lock time increases
Solution Approach 1:
The calibration process is performed in advance during manufacturing or system initialization, not during normal PLL operation. The calibration data is stored and reused for gain compensation during lock acquisition. This approach ensures frequency and phase accuracy without repeatedly performing time-consuming calibration sequences during lock operations, thereby minimizing impact on PLL lock time.
Solution Approach 2:
The patent implements feedback by using the calibrated gain information to continuously adjust the DCO control word during PLL operation. The system monitors the phase error and applies gain compensation based on pre-characterized calibration data, enabling accurate frequency and phase locking without requiring extended lock times for repeated calibration measurements.
3Adaptability or versatility
If calibration logic is added to normalize DCO codeword gain, then performance across PVT conditions improves, but circuit footprint increases
Solution Approach 1:
The patent extracts the calibration functionality into a separate calibration circuit module that operates independently from the main PLL signal path. The calibration circuit determines DCO gain characteristics and stores calibration data in memory, while the main PLL uses this pre-stored data for compensation. This separation allows comprehensive PVT coverage without requiring the entire calibration apparatus to be active during normal operation, thereby reducing the effective circuit footprint during operational modes.
Solution Approach 2:
The calibration circuit is designed to be multi-functional, serving both characterization and compensation functions. The same calibration infrastructure is used to determine gain under various PVT conditions and to provide ongoing compensation during operation. This universal approach maximizes adaptability across PVT conditions while minimizing the additional circuit footprint compared to having separate dedicated circuits for each function.
Data Source
AI summary
A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.