Digital Oscillator Jitter Shaping for Mixed-Signal Sampling Clocks
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Solution Overview
Problem
Existing digitally controlled oscillators (DCOs) are inefficient in shifting low-frequency digital jitter out of the bandwidth of interest in mixed signal circuits, leading to performance issues in analog-to-digital and digital-to-analog converters, as they do not effectively suppress jitter in the low-frequency range.
Innovation Solution
A digitally controlled oscillator with a jitter shaping circuit that accumulates error in edge placement and uses a clock advancement mechanism to shift low-frequency digital jitter into higher frequency jitter, utilizing an overflow counter, frequency control adder, DCO accumulator, and error resolution circuit to generate an output clock with reduced jitter within the bandwidth of interest.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional DCO followed by an APLL is used to reduce jitter, then jitter suppression in bandwidth of interest is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the jitter shaping function from the traditional APLL and implements it directly within the DCO using digital circuitry. The jitter shaping accumulator and clock advancement circuit are integrated into the DCO structure, separating the jitter reduction function from the frequency synthesis function, thereby reducing overall device complexity while maintaining jitter suppression performance
Solution Approach 2:
The patent replaces the analog APLL mechanism with a digital jitter shaping circuit that uses accumulators and logic circuits to achieve the same jitter reduction effect. This substitution of analog components with digital components simplifies the overall system architecture and reduces power consumption while maintaining the reliability benefit of jitter suppression
2Reliability
If a traditional DCO followed by an APLL is used to reduce jitter, then jitter suppression in bandwidth of interest is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the power-hungry analog APLL with a digital jitter shaping circuit consisting of accumulators and logic elements. This substitution dramatically reduces power consumption while maintaining the jitter suppression function, as digital circuits at the DCO frequency consume significantly less power than analog phase-locked loop components
3Device complexity
If DCO generated clock is used directly as sampling clock, then device size and power are reduced, but jitter in bandwidth of interest degrades circuit performance
Solution Approach 1:
The patent merges the jitter shaping function with the DCO by integrating the jitter shaping accumulator and clock advancement circuit directly into the DCO structure. This combination allows the DCO to simultaneously perform frequency synthesis and jitter reduction, eliminating the need for separate APLL circuitry and reducing overall device size while maintaining circuit performance
Solution Approach 2:
The patent extracts the essential jitter reduction function from the APLL and implements it within the DCO using digital accumulation and clock advancement mechanisms. This extraction allows the system to achieve jitter suppression without the overhead of a complete APLL, reducing device complexity while preserving circuit performance
Data Source
AI summary
A digitally controlled oscillator (DCO) generating an output clock includes a jitter shaping module for shifting low frequency digital jitter on the output clock into higher frequency jitter.