DCO Phase Modulator Timing Skew for Linear Frequency Control
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Solution Overview
Problem
Modern communication systems require oscillators with wide bandwidth and low output distortion, which existing polar-type digital transmitters with multiple capacitor banks in their tank circuits cannot adequately provide due to non-linear frequency responses caused by varying sensitivity characteristics of capacitors.
Innovation Solution
A linearization method and circuit that adjusts the frequency control word (FCW) for a digitally controlled oscillator (DCO) by interpolating between reference output FCWs and considering the sensitivity characteristics of multiple capacitor banks, ensuring a linearized frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple capacitor banks are used in the tank circuit to control frequency, then frequency control capability is improved, but non-linear frequency response and output distortion increase due to varying sensitivity characteristics
Solution Approach 1:
The patent applies preliminary linearization by pre-calculating and storing correction values in a lookup table that compensates for the non-linear sensitivity characteristics of capacitor banks. Before frequency control operation, the system loads these pre-computed correction factors into the lookup table, allowing real-time linearization without complex calculations during frequency modulation.
Solution Approach 2:
The patent introduces a lookup table as an intermediary component between the frequency control input and the capacitor bank selection. This lookup table acts as a mediator that translates the desired frequency into the appropriate capacitor configuration, compensating for non-linearities without requiring direct complex control logic.
2Productivity
If high modulation rates are used to meet modern communication requirements, then communication speed is improved, but output distortion increases due to oscillator non-linearities
Solution Approach 1:
The system performs preliminary linearization correction by consulting the lookup table before generating the actual frequency control signal. This pre-correction ensures that even at high modulation rates, the frequency output remains linear and free from distortion caused by capacitor bank non-linearities.
Solution Approach 2:
The patent implements a feedback mechanism where the actual oscillator output is monitored and compared against the desired frequency. The lookup table is used to generate correction signals based on this feedback, continuously compensating for non-linearities and reducing output distortion during high-rate modulation.
3Adaptability or versatility
If wide bandwidth is implemented to meet modern communication needs, then frequency range is improved, but frequency control precision deteriorates due to capacitor sensitivity variations
Solution Approach 1:
The lookup table is pre-populated with correction values that account for capacitor sensitivity variations across the entire operating bandwidth. This preliminary preparation ensures that regardless of which frequency within the wide bandwidth is selected, the appropriate correction is immediately available, maintaining precision throughout the full frequency range.
Solution Approach 2:
The patent changes the control parameter from direct frequency specification to lookup table index selection. By mapping the desired frequency to a pre-calculated correction value in the lookup table, the system maintains precise frequency control across wide bandwidth variations without being affected by capacitor sensitivity drift.
Data Source
AI summary
An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.