DCT DST Computation Circuit Reducing Latency and Power
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Solution Overview
Problem
Existing computation circuits for discrete cosine transform (DCT), discrete sine transform (DST), inverse discrete cosine transform (IDCT), and inverse discrete sine transform (IDST) face challenges in reducing delay and routing complexity, leading to high latency and power consumption.
Innovation Solution
A computation circuit design incorporating a first term computation circuit, a second term computation circuit, a third term computation circuit, a 2's complement computation circuit, and a second adder, which includes higher-bit and lowest bit computation circuits with shift control signals and zero detection mechanisms to optimize bit shifting and sign determination, reducing unnecessary computations when the multiplicand is zero.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computation circuits are used for DCT, DST, IDCT and IDST, then the transforms can be performed, but the circuit complexity and delay increase
Solution Approach 1:
The computation circuit is divided into multiple term computation circuits (first term, second term, third term computation circuits), each handling specific parts of the DCT/DST computation. This segmentation allows parallel processing of different computational terms, reducing overall computation delay while maintaining modular circuit design.
Solution Approach 2:
The circuit employs dynamic shift control signals that selectively perform left-shift operations on multiplicands based on multiplier values. The effective level control signals dynamically enable or disable computation paths, allowing the circuit to adapt its complexity to the actual computation requirements, reducing unnecessary operations.
2Reliability
If full computation paths are always active, then computation accuracy is maintained, but power consumption increases
Solution Approach 1:
The circuit activates only the necessary computation paths based on the actual input values and required precision. The effective level control signals enable partial computation by selectively activating higher-bit or lowest bit computation circuits, performing only the minimum necessary operations to achieve accurate results, thus reducing power consumption while maintaining reliability.
3Measurement precision
If 2's complement computation is performed on all bits, then sign handling is accurate, but computation delay increases
Solution Approach 1:
The circuit extracts and handles the sign information separately from the magnitude computation. The bit sign control signals and lowest bit sign control signals determine signs independently, allowing the main computation paths to focus on magnitude calculations without unnecessary 2's complement operations on all bits, thereby reducing delay while maintaining sign accuracy.
Data Source
AI summary
The present invention discloses a computation circuit. Each of a first and a second term computation circuits includes higher bit computation circuits, a lowest bit computation circuit and a first adder. Each of the higher bit computation circuits left-shifts a multiplier, outputs the effective shifted multiplier having a sign determined and further performs left-shifts without performing 2's complement computation to generate a higher bit computation result. The lowest bit computation circuit outputs the effective multiplier having the sign determined to generate a lowest bit computation result. The first adder adds the bit computation results to generate a term computation result. The third term computation circuit outputs an effective addend having the sign determined and adds the addend to the summation of a number of 2's complement to generate a third term computation result. The second adder adds the term computation results and the third term computation result to generate a total computation result.