Discrete Cosine Transform Pipeline Using Shift-Add Arithmetic
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Solution Overview
Problem
Existing discrete cosine transform (DCT) implementations in signal processing systems require floating point multiplication operations, which are slow and power-consuming, posing challenges in devices with limited resources like mobile multimedia devices.
Innovation Solution
A method and system for approximating DCT using a multi-stage pipeline that performs data transformations without multipliers, utilizing shift and addition operations to represent power-of-two coefficients, thereby reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating point multiplication operations are used in DCT implementation, then transformation accuracy is maintained, but execution speed decreases and power consumption increases
Solution Approach 1:
The patent changes the parameter representation from floating-point to fixed-point arithmetic, and further to integer arithmetic with power-of-two coefficients. This parameter change allows multiplication operations to be replaced with bit-shift operations, significantly improving execution speed and reducing power consumption while maintaining sufficient transformation accuracy for signal processing applications
Solution Approach 2:
The patent substitutes the mechanical multiplication operation with a bit-shift operation. By representing coefficients as powers of two, the multiplication is replaced by simple bit-shifting, which is much faster and more power-efficient in hardware implementation while preserving the essential mathematical function of the DCT transformation
2Measurement precision
If floating point multiplication operations are used in DCT implementation, then transformation accuracy is maintained, but device area increases
Solution Approach 1:
The patent changes the parameter representation from floating-point to fixed-point to integer arithmetic. This parameter change eliminates the need for complex floating-point multiplication hardware, reducing the hardware area significantly while maintaining sufficient transformation accuracy for practical signal processing applications
Solution Approach 2:
The patent substitutes complex multiplication hardware with simple bit-shift circuits. By representing coefficients as powers of two, the hardware implementation replaces large-area multiplier units with compact shift registers and adders, dramatically reducing the overall device area while preserving the essential DCT functionality
3Measurement precision
If floating point operations are used in DCT implementation, then transformation accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent changes the arithmetic parameter from floating-point to integer representation. This parameter change enables the use of simpler, more power-efficient integer arithmetic units instead of power-hungry floating-point units, significantly reducing power consumption while maintaining sufficient accuracy for mobile multimedia applications
Solution Approach 2:
The patent substitutes power-consuming floating-point multiplication with low-power bit-shift operations. By representing coefficients as powers of two, the implementation replaces high-power multiplier circuits with minimal-power shift and add circuits, dramatically reducing overall power consumption while preserving the essential DCT transformation capability
Data Source
AI summary
A processor includes a multi-stage pipeline having a plurality of stages. Each stage is capable of receiving input values and providing output values. Each stage performs one of a plurality of data transformations using the input values to produce the output values. The data transformations collectively approximate at least one of: a discrete cosine transform and an inverse discrete cosine transform. The stages do not use any multipliers to perform the data transformations.