16-Point DCT Unit for Video Encoding Chip Area Reduction
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Solution Overview
Problem
Existing data compression techniques require separate implementations for different sizes of discrete cosine transforms (DCTs), leading to increased chip area and power consumption due to the need for multiple DCT implementations for various block sizes in video encoding and decoding processes.
Innovation Solution
A 16-point DCT implementation that can perform DCTs of multiple sizes, including 16, 8, and 4-point DCTs, allowing for concurrent operation of different sized DCTs to reduce the need for separate implementations, thereby consuming less board space and promoting energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate DCT implementations are used for different block sizes (16x16, 8x8, 4x4), then each transform size can be optimized independently, but the total chip area and power consumption increase significantly
Solution Approach 1:
The patent implements a universal 16-point DCT core that can perform multiple DCT operations of different sizes (16x16, 8x8, 4x4) by selectively enabling different processing paths. The same hardware infrastructure handles all transform sizes, eliminating the need for separate dedicated DCT units for each block size while maintaining optimization for each specific transform type.
Solution Approach 2:
The patent structures the DCT implementation hierarchically where 8x8 DCT is nested within the 16-point DCT framework, and 4x4 DCT is nested within the 8x8 DCT framework. This nested structure allows smaller transform operations to share the same computational resources and processing pipeline as larger transforms, reducing overall hardware requirements while preserving the mathematical correctness of each transform size.
2Productivity
If multiple separate DCT implementations are deployed to support various video block sizes, then all block sizes can be processed efficiently, but power consumption increases due to redundant circuitry
Solution Approach 1:
The patent creates a single multi-functional DCT processing unit that can efficiently handle 16x16, 8x8, and 4x4 video blocks by configuring the same hardware resources for different transform sizes. This eliminates redundant circuitry that would exist in separate dedicated DCT implementations, thereby reducing power consumption while maintaining processing efficiency for all block sizes through optimized resource utilization.
3Area of stationary object
If a single 16-point DCT implementation is used for all block sizes, then chip area is reduced, but the ability to perform optimized transforms for smaller blocks is lost
Solution Approach 1:
The patent segments the 16-point DCT processing into configurable paths that can be selectively activated based on the input block size. The processing pipeline is divided into stages that can be dynamically enabled or disabled to match the required transform size, allowing the same hardware to adapt to 16x16, 8x8, or 4x4 blocks while maintaining optimized processing characteristics for each size through selective path activation.
Data Source
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AI summary
In general, techniques are described for implementing a 16-point discrete cosine transform (DCT) that is capable of applying multiple IDCT of different sizes. For example, an apparatus comprising a 16-point discrete cosine transform of type II (DCT-II) unit may implement the techniques of this disclosure. The 16-point DCT-II unit performs these DCTs-II of different sizes to transform data from a spatial to a frequency domain. The 16-point DCT-II unit includes an 8-point DCT-II unit that performs one of the DCTs-II of size 8 and a first 4-point DCT-II unit that performs one of the DCTs-II of size 4. The 8-point DCT-II unit includes the first 4-point DCT-II unit. The 16-point DCT-II unit also comprises an 8-point DCT-IV unit that includes a second 4-point DCT-II unit and a third 4-point DCT-II unit. Each of the second and third 4-point DCT-II units performs one of the DCTs-II of size 4.